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41 Commits

Author SHA1 Message Date
Abdelatif Guettouche
2273684cb1 esp32/esp32_spi.c: Use device specific locks. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-10-16 00:01:23 -07:00
Gustavo Henrique Nihei
e13dd7dab9 arch/xtensa: Remove FAR qualifier for Xtensa-specific files 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2021-09-22 08:16:01 -03:00
Abdelatif Guettouche
79cc12c034 arch/xtesna/esp32: Merge the contents of esp32_cpuint and esp32_irq. 
They do the same thing (manipulate interrupts) keeping them separated
was making things harder.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
02c17c3169 arch/esp32: Simplify the interrupt allocation process. 
Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
eefe7ebe5f xtensa/esp32_cpuint: export only one function to allocate a CPU 
interrupt.

That function will have a parameter to decide whether to allocate a
level sensitive interrupt or an edge sensitive interrupt.

All the drivers are also updated with this API change.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-26 07:06:22 +09:00
Abdelatif Guettouche
56a7f3b651 arch/xtensa/esp32: Update the drivers regarding the API change in IRQ 
handling.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
5be9f24fe5 arch/xtensa/esp32: Disable the CPU interrupt right when it's alloacted. 
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-20 13:17:25 -03:00
Abdelatif Guettouche
4f2f2ef9fb arch/xtensa: Get the cpu member out of the read only structure. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Abdelatif Guettouche
3e44c347fd arch/xtensa/esp32_spi&i2c: Get the CPU index when attaching an 
interrupt.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2021-08-03 19:52:12 -07:00
Sara Souza
857414e95d xtensa/esp32: expose SPI2 as a char driver 2021-07-27 09:55:49 -07:00
Xiang Xiao
2e54df0f35 Don't include assert.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-03 08:36:03 -07:00
Xiang Xiao
d7f96003cf Don't include debug.h from public header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-06-01 06:42:02 +09:00
Gustavo Henrique Nihei
4d4250fcca xtensa/esp32: Improve SPI polling to use the entire HW buffer 2021-04-08 23:36:28 -05:00
Gustavo Henrique Nihei
2d0e690803 xtensa/esp32: Refactor register access functions on SPI driver 2021-04-01 17:13:55 -03:00
Gustavo Henrique Nihei
77c5995f93 xtensa/esp32: Use essential boolean expressions on condition statements 2021-03-30 01:23:02 -05:00
Gustavo Henrique Nihei
5e8eb420b7 xtensa/esp32: Fix MISO/MOSI data length field configuration 
Both fields were being configured with the total number of remaining
bytes instead of the number of bytes actually bound to DMA descriptors.
 2021-03-30 01:23:02 -05:00
Gustavo Henrique Nihei
b4dbae1b10 xtensa/esp32: Commit setbits configuration before SPI transaction 
The motivation is to avoid consistency issues when using Mixed Mode
(i.e. Polling and Interrupt/DMA transfers being used interchangeably)
 2021-03-30 01:23:02 -05:00
Gustavo Henrique Nihei
4d877abf3f xtensa/esp32: Avoid incrementing a NULL pointer for RX buffer 2021-03-30 01:23:02 -05:00
Gustavo Henrique Nihei
a27d5b1063 xtensa/esp32: Remove useless pointer check in SPI DMA exchange 2021-03-30 01:23:02 -05:00
Gustavo Henrique Nihei
eb505ed866 xtensa/esp32: Fix DMA burst mode being unintendedly disabled 2021-03-26 23:39:53 -05:00
Gustavo Henrique Nihei
e4efa9dfa7 xtensa/esp32: Fix interrupt flag configuration for DMA transfers 
Previously SPI interrupts were enabled on DMA initialization. But since
the addition of SPI Mixed mode it created a side-effect, breaking
polling transfers. So now interrupts are enabled before the DMA
transactions and disabled once they are finished.
Furthermore, the transaction done flag is also cleared before a new
transaction starts.
 2021-03-21 00:16:59 -07:00
Gustavo Henrique Nihei
20d24fe148 xtensa/esp32: Fix esp32_spi_setbits for Polling when DMA is also enabled 
Commit 6382b2ba introduced the possibility of using SPI in Mixed mode,
i.e. performing SPI transfers via both polling and interrupts. However,
setbits was only applying the configuration if DMA was not enabled.
 2021-03-21 00:16:59 -07:00
Gustavo Henrique Nihei
bfc551484a xtensa/esp32: Clean up esp32_dma_init code 
Removed "isrx" parameter whose only purpose is to trigger an assertion
on DEBUG builds. Also performed a minor refactor.
 2021-03-20 19:23:44 -07:00
Gustavo Henrique Nihei
dc7a0b0a5c xtensa/esp32: Use Polling instead of DMA for transfers below threshold 
Also refactored code to remove a confusing duplicate "dma_chan" field
which had the same purpose of the "use_dma" boolean.
 2021-03-19 23:13:32 -07:00
chenwen
19627095e4 esp32/esp32_allocateheap.c: Support the maximum available internal heap configuration 2021-03-02 18:27:20 -08:00
Alan C. Assis
f56ff40101 Add esp32_gpio_matrix_in/out to replace ROM functions 2021-02-11 20:39:51 +00:00
Dong Heng
eb2937003b xtensa/esp32: Fix ESP32 SPI driver issues 
1. reset SPI hardware when deinitializing
2. reset SPI priavte configuration data when deinitializing
3. free interrupt when deinitializing
 2021-01-18 12:54:12 +01:00
YAMAMOTO Takashi
a24f66f31f arch/xtensa/src/esp32/esp32_spi.c: Fix a syslog format 2020-11-22 19:01:05 -08:00
Alan C. Assis
d11f02d772 xtensa/esp32: Fix remaining SEPARATE typo 2020-11-06 16:19:48 +01:00
Juha Niskanen
a01a01ab45 arch: spi: fix typos and run nxstyle 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2020-10-31 10:40:41 -07:00
Dong Heng
a12a79fdb3 xtensa/esp32: Fix SPI master DMA RX buffer memcpy size error 2020-10-29 11:51:05 +01:00
Abdelatif Guettouche
9b98f20969 arch/xtensa: Fix the naming of the internal heap functions. They should 
be prefixed by xtensa_ instead of up_.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
5ac5655fa4 arch/xtensa/src/esp32/esp32_spi&spiflash: Free the correct buffer. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
172896728f arch/xtensa/src/esp32/esp32_spi.c: Instead of returning with no error 
code, assert the return of the imm_malloc function.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
1b12d20225 arch/xtensa/src/esp32/esp32_spiflash.c&esp32_spi.c: Allocate a buffer from DRAM 
when the given buffer is from PSRAM.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-10-25 20:20:01 -03:00
Abdelatif Guettouche
d1225f3110 arch/xtensa/src/esp32: Use the same function numbering as the TRM. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2020-10-07 11:52:04 -03:00
saramonteiro
a562fba971 ESP32: Fixed the type of cpuint variables in esp32_emac.c esp32_i2c.c esp32_spi.c esp32_spi_slave.c 2020-10-02 09:57:56 -07:00
Ouss4
3560e16ac7 arch/xtensa/src/esp32/esp32_spi.c: When the TX buffer is empty send 
something to kick off the SPI clock.
 2020-09-04 17:43:51 -03:00
Ouss4
37d8799d07 arch/xtensa/src/esp32/esp32_spi.c: spi_cmddata function will be defined 
by board logic, don't need it here.
 2020-08-27 14:12:34 +08:00
Dong Heng
39539be149 xtensa/esp32: Improve SPI transmission 
Master:
  1. add DMA RX/TX support
  2. add software chip selection
  3. add user defined chip selection
  4. add IOMUX check and IO map

Slave:
  1. add DMA RX/TX support
  2. add IOMUX check and IO map
  3. use full 256 bit SPI TX/RX cache in non-DMA mode
 2020-08-21 10:04:27 +01:00
Alan C. Assis
79a3fd1932 ESP32: Add driver support to SPI Master and Slave 
This driver was implemented by Dong Heng <dongheng@espressif.com>
and modified to fix coding style by Alan Carvalho de Assis.
 2020-07-19 21:26:58 +01:00