In protected build mode, the syscall returns without setting correct value for the CONTROL register, which causes the userspace threads working in privileged mode after syscall.
Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
Currently concerns only arm.
tools/ci/testlist/msys2.dat:
At the moment I only added the board nucleo-l152re:nsh
.github/workflows/build.yml:
Enabled cmake for msys2
since not all Armv7-m platform support double-precision floating
operations, so we add an extra option that help those specific platform
could define the single-precision floating operations.
for example, qemu-mps platform(armv7-m) support double-precision
floating operations, so we do not need to open
CONFIG_ARM_FPU_SINGLE_HARDWARE build options;
but for fc7300 platform(armv7-m) only support single-precision floating
operations, so if we pass "-fhard" build option to "ghs" compiler, then
the following instruction will be generated:
vcvt.f64.s32 d9, s18
which will fail to execute on fc7300 platform.
with "-fsingle" build option, the "ghs" compiler will generate hardware
instruction for single-precision floating operation, and generate
software instruction for double-precision floating operation.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
To support greenhill compilation, LDFLAGS removes the code that adds -T through addprefix to ARCHSCRIPT(greenhill requires a space between -T and ldscript files, but addprefix didn't do it). However,if we modified like this, when ARCHSCRIPT has more than one ldscript, the -T is only added to the first ldscript, but not to the following ldscripts, which results in a warning when linking.
To solve this problem, we can just add a space after $(SCRIPT_OPT) when using addprefix, instead of deleting addprefix.
Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
Only in the non-critical region， nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be released
we also need keep restore_critical_section in svc call
test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
-machine virt,virtualization=on,gic-version=3 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
armv7-m/arm_mpu.c: In function 'mpu_dump_region':
armv7-m/arm_mpu.c:621:13: warning: format '%X' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int' [-Wformat=]
621 | _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv7-m/arm_mpu.c:621:13: warning: format '%X' expects argument of type 'unsigned int', but argument 6 has type 'long unsigned int' [-Wformat=]
621 | _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv7-m/arm_mpu.c:621:13: warning: format '%X' expects argument of type 'unsigned int', but argument 7 has type 'long unsigned int' [-Wformat=]
621 | _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv7-m/arm_mpu.c:621:13: warning: format '%u' expects argument of type 'unsigned int', but argument 8 has type 'long unsigned int' [-Wformat=]
621 | _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
Modified the input parameters of mpu_initialize to require the caller to provide the number of entries in the table
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Summary:
1.Modify the conditions for entering different include header files
2.Added pre-definition for _Atomic _Bool when it is missing
3.Added nuttx for stdatomic implementation. When toolchain does not support atomic, use lib/stdatomic to implement it
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Execute data and instruction sync barriers after writing MPU register,
to ensure MPU setting take effects that the new changes are seen.
testing in lm3s6965-ek:qemu-protected
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
According to the current design on the armv7-a platform,
only fiq is processed in TEE, while irq and fiq are processed
in REE.
If we enable the irq function in TEE, when we process
some signal-related scenarios in TEE,
such as the ostest sighand testcase, this testcase will
call up_irq_enable() to enable irq interrupt in the
arm_sigdeliver() function. After the signal processing
logic is executed, irq will be disabled again.
During the interval of enabling irq, some external device
irq interrupts will be enabled, but these external device
irqs do not have corresponding handlers registered in TEE,
so an "unexpected irq isr exception" will be triggered.
Therefore, a better implementation is to keep the original
implementation of the up_irq_enable() function, that is,
to enable only fiq in TEE and to enable irq and fiq in REE.
Then for vendor-specific requirements, such as the need to
briefly enable irq during the TEE initialization process
and then disable irq before starting APz in TEE, we directly
provide a separate implementation of enabling irq in the
vendor, without modifying the implementation of the public
up_enable_irq() function.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
CC: unistd/lib_setregid.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 53: warning #193-D:
zero used for undefined preprocessing identifier "NR_IRQS"
# if NR_IRQS <= 256
^
"/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 82: warning #193-D:
zero used for undefined preprocessing identifier "NR_IRQS"
#if NR_IRQS <= 256
CC: mount/fs_umount2.c "/mnt/yang/qixinwei_vela_warnings_04_23/nuttx/include/nuttx/irq.h", line 72: warning #193-D:
zero used for undefined preprocessing identifier "NR_IRQS"
#if NR_IRQS <= 256
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
the greenhills compiler provide its own implementation of va_start,
va_end, va_arg, va_copy. so if we are build vela with greenhills
compiler, we should using the stdarg implementation provided by
greenhills, not our own
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Pass CP15_CACHE_INVALIDATE argument with r1 register to cp15_dcache_op_level.
cache level is 0(L1 D-Cache) with r0 register.
prototype:
void cp15_dcache_op_level(uint32_t level, int op)
Signed-off-by: Jinliang Li <lijinliang1@lixiang.com>
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
argument to macro is empty
SP_DSB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
argument to macro is empty
SP_DMB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 252: warning #76-D:
argument to macro is empty
SP_DSB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 261: warning #76-D:
argument to macro is empty
SP_DMB();
^
"/mnt/yang/qixinwei_vela_warnings/nuttx/include/nuttx/spinlock.h", line 296: warning #76-D:
argument to macro is empty
SP_DSB();
^
Signed-off-by: yanghuatao <yanghuatao@xiaomi.com>
according to armv6-m/armv7-m arch reference manual:
the three ISB {<opt>}, DSB {<opt>}, DMB {<opt>} instructions <opt>
field are defined as:
Specifies an optional limitation on the ISB/DSB/DMB operation. Allowered
values are:
Full system ISB/DSB/DMB operation, encoded as option=='1111'. Can be
omitted.
All other encodings of the options are RESERVED.
the "#opt" field of "isb #opt"
So we could remove the options field in Armv7-m platform.
The following are the build error with greenhills compiler:
CC: common/arm_exit.c [asarm] (error #2071) /tmp/gh_001h70j1.si 92: bad parameter
isb 15
------^
[asarm] (error #2071) /tmp/gh_001h70j1.si 112: bad parameter
isb 15
------^
[asarm] (error) errors during processing
According to armv8-m arch reference manual:
the ISB/DMB instruction's "opt" encoding rule is same as
armv6-m/armv7-m, but the "DSB" instruction is different, in armv8-m, the
"DSB {<opt>}" field has two valid encoding options: 0b0000, 0b0100.
and all other encoding options are reserved.
In Armv7-a/Armv8-a, the dsb/dmb option field has 8 valid state value.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
