Xiang Xiao
fcc48c2254
arch/arm: Don't include arch/arch.h in include/irq.h
...
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:25:56 +03:00
Xiang Xiao
7c5b2e3305
arch/arm: Remove FAR and CODE from common/ and arm*/ folder
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-04-19 00:23:59 +03:00
Huang Qi
edef327655
arch/arm: Move ARCHCPUFLAGS to Toolchain.defs
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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-19 02:24:00 +08:00
chao.an
7b9978883c
arch/arm: optimize context switch speed
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The current context save implementation saves registers of each task
to xcp context, which is unnecessary because most of the arm registers are
already saved in the task stack, this commit replace the xcp context with
stack context to improve context switching performance and reduce the tcb
space occupation of tcb instance.
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-03-15 23:03:51 +09:00
Xiang Xiao
0c7517e579
arch: Remove the duplicated syscall.h in each arch
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-27 22:54:13 +08:00
Xiang Xiao
25213c42a5
arch/arm: Remove the empty spinlock.h file
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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-25 09:18:53 +09:00
chao.an
0a8d951837
arch/arm: correct the frame pointer register declare
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In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code.
In AArch64, the frame pointer is stored in register X29.
Signed-off-by: chao.an <anchao@xiaomi.com>
2021-08-19 01:26:07 -07:00
chao.an
6c40185985
arm/v7-a/fpu: add VFP-v3 D32 support
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Signed-off-by: chao.an <anchao@xiaomi.com>
2021-05-21 09:55:00 -03:00
Alin Jerpelea
c39339a7a8
arch: arm: include: nxstyle fixes
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nxstyle fixes to pass CI
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-22 19:28:38 -07:00
Alin Jerpelea
4daa276903
arch: arm: include: Author Gregory Nutt: update licenses to Apache
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Gregory Nutt has submitted the SGA and we can migrate the licenses
to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-22 19:28:38 -07:00
Xiang Xiao
335ba21657
arch/arm: Fix syscall number out of swi range in thumb mode
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The immediate number is 8bits in thumb mode:
+---------------------+---------------+
|15 14 13 12 11 10 9 8|7 6 5 4 3 2 1 0|
+---------------------+---------------+
| 1 1 0 1 1 1 1 1| imm8 |
+---------------------+---------------+
The immediate number is 24bits in arm mode:
+-----------+-------------------------------------------------------------------------+
|31 30 29 28|27 26 25 24|23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0|
+-----------+-----------+-------------------------------------------------------------+
| cond | 1 1 1 1| imm24 |
+-----------+-----------+-------------------------------------------------------------+
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Change-Id: I62503cdc377fcee81864e88e981d389bce2e1b45
2021-03-17 14:52:58 -03:00
Nathan Hartman
679b4fbee2
arch: Fix included directed -> included directly
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This typo had been copied and pasted into numerous irq and syscall
headers.
2020-04-05 22:31:15 +01:00
Gregory Nutt
abf6965c24
Squashed commit of the following:
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libs/: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
syscall/: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
wireless/: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
Documentation/: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
include/: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
drivers/: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
sched/: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
configs: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
arch/xtensa: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
arch/z80: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
arch/x86: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
arch/renesas and arch/risc-v: Remove references to CONFIG_DISABLE_SIGNALS. Signals can no longer be disabled.
arch/or1k: Remove all references to CONFIG_DISABLE_SIGNALS. Signals are always enabled.
arch/misoc: Remove all references to CONFIG_DISABLE_SIGNALS. Signals are always enabled.
arch/mips: Remove all references to CONFIG_DISABLE_SIGNALS. Signals are always enabled.
arch/avr: Remove all references to CONFIG_DISABLE_SIGNALS. Signals are always enabled.
arch/arm: Remove all references to CONFIG_DISABLE_SIGNALS. Signals are always enabled.
2019-04-29 14:52:05 -06:00
Gregory Nutt
b1001b4e50
Update TODO list regarding non-queuing of signal actions; Add comments in code at areas where the issue applies.
2019-02-04 08:35:03 -06:00
Xiang Xiao
9f408e9937
arch/arm/src/include/xxx/syscall.h: Align semi-hosting call style with other syscalls
2019-01-26 07:40:47 -06:00
Gregory Nutt
0001607f71
arch/arm: (1) Add semihost support for syslog, (2) Add semihost support for HostFS
2018-08-23 08:00:07 -06:00
Gregory Nutt
9222f50e1c
arch/: Make sure the up_irq_enable() is available on all architectures. I will not be able to test all of these new versions of this function so this may break things for awhile.
2018-06-06 09:25:40 -06:00
Gregory Nutt
26560cb9e1
i.MX6: Remove non-cached, inter-cpu memory region. Not a useful concept.
2016-12-13 16:59:50 -06:00
Gregory Nutt
3353d9280f
i.MX6: Disable non-cached region support. Add SCU register definitions.
2016-11-26 17:03:57 -06:00
Gregory Nutt
6ff6da083f
Fix a few compile related issues from the last commit
2016-11-26 12:23:09 -06:00
Gregory Nutt
aae306e942
i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region.
2016-11-26 12:04:02 -06:00
Gregory Nutt
666cc280f4
Rename irqenable() to up_irq_enable(); rename irqdisable() to up_irq_disable()
2016-02-14 16:54:09 -06:00
Gregory Nutt
83bc1c97c3
Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore()
2016-02-14 16:11:25 -06:00
Gregory Nutt
bacf7cf07e
ARMv7-R: fix some issues to get a clean compilation; TMS570: Add enough logic to support a minimum build. Not much there on the initial commit
2015-12-16 09:03:14 -06:00
Gregory Nutt
36726b1bc4
Standardize the width of all comment boxes in header files
2015-10-02 17:42:29 -06:00
Gregory Nutt
29136e51cc
Clean up and review of header files for conformance to standards
2015-06-12 19:26:01 -06:00
Gregory Nutt
ae15c6963c
Make some file section headers more consistent with standard
2015-04-08 08:04:12 -06:00
Gregory Nutt
d8561fbcae
Remove execute privileges from some header files
2015-02-01 06:24:18 -06:00
Gregory Nutt
9aae0adffa
If we are configured to use a kernel stack while in SYSCALL handling, then we need to switch back to the user stack to deliver a signal
2014-09-15 11:38:48 -06:00
Gregory Nutt
946b916f69
Initial integration of kernel stack (does not work)
2014-09-14 11:19:34 -06:00
Gregory Nutt
16ddffc941
Add the initial implementation of the process kernel stack logic. Not yet integrated into the main OS logic nor tested.
2014-09-14 09:53:54 -06:00
Gregory Nutt
ffff51c1b1
Rename everything associated with the dynamic process stack to ustack to make room in the name space for a kstack
2014-09-14 09:10:09 -06:00
Gregory Nutt
006cf7d745
Add logic to initialize the per-process user heap when each user process is started
2014-09-10 15:55:36 -06:00
Gregory Nutt
12775801c9
Add support for delivery of use-mode signals in the kernel build.
2014-09-02 15:58:14 -06:00
Gregory Nutt
e11679acf8
Rename CONFIG_NUTTX_KERNEL to CONFIG_BUILD_PROTECTED; Partially integrate new CONFIG_BUILD_KERNEL
2014-08-29 14:47:22 -06:00
Gregory Nutt
db69d94935
Fix ARM7/9 and Cortex-A SYSCALLs: For threads in SVC mode, the SVC instructions clobbers R14. This must be taken account in the inline assembly
2014-08-29 10:07:11 -06:00
Gregory Nutt
8dd679e875
ARMv7-A: Add SYSCALL handling logic
2014-08-28 14:52:14 -06:00
Gregory Nutt
cb8e081dba
Mostly cosmetic use of uintptr_t to hold addresses instead of uint32_t
2014-08-26 10:44:10 -06:00
Gregory Nutt
699a54a022
Misc changed to get the SAMA5 ELF configuration with address environments working
2014-08-25 13:28:13 -06:00
Gregory Nutt
8907616478
Cortex-A/SAMA5 address environment support is code complete (untested)
2014-08-25 11:18:32 -06:00
Gregory Nutt
95c79c675c
Add addrenv.h; First cut at Cortex-A address environment structures; Add configuration options to setup address enviornment
2014-08-24 09:57:53 -06:00
Gregory Nutt
0a134f0158
Need to enable FIQ in initial task state; Improve H32/64 test in IRQ handling
2014-06-21 09:55:09 -06:00
Gregory Nutt
c68d2532be
SAMA5D4: Add support for secure/FIQ interrupts; SAIC supports need to be be enabled unconditionally
2014-06-20 18:16:41 -06:00
Gregory Nutt
25d4ff745b
More trailing whilespace removal
2014-04-13 16:22:22 -06:00
Gregory Nutt
0673a9564c
Oops. Mnemonic changed from SWI to SVC in cortex A
2014-01-05 15:59:49 -06:00
Gregory Nutt
b9816723a5
Add ARMv7-A syscall.h header file
2014-01-05 15:49:06 -06:00
Gregory Nutt
8695c89aa4
SAMA5: Modification of some CPSR-related inline functions
2013-07-31 09:11:24 -06:00
Gregory Nutt
b75a0cf8be
Add ARMv7-A irqdisable() inline function
2013-07-30 11:37:09 -06:00
Gregory Nutt
cb3f394d53
Improve some ARMv7-A/M floating point register save time; Add floating point register save logic for ARMv7-A
2013-07-23 17:52:06 -06:00
Gregory Nutt
ca9b52b07f
SAMA5/Cortex-A: Improve irqsave/restore inlines + add irqenable. Add skeleton file for SAMA5 interrupt management. Also change from last commit that was left in the editor
2013-07-21 17:08:40 -06:00