Commit Graph

1379 Commits

Author SHA1 Message Date
Gustavo Henrique Nihei
f462be5365 risc-v/espressif: Fix NULL-dereferencing in WDT interrupt handling
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-28 22:39:00 +03:00
Gustavo Henrique Nihei
6647f194db risc-v/espressif: Update revision of esp-hal-3rdparty
Small cleanup, no added features.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-28 14:43:40 -03:00
Xiang Xiao
bc3e6c84e1 arch: Rename up_[early]serialinit to [arm64|riscv|x86_64][early]serialinit
The naming standard at:
https://cwiki.apache.org/confluence/display/NUTTX/Naming+of+Architecture%2C+MCU%2C+and+Board+Interfaces
requires that all MCU-private function begin with the name of the architecture, not up_.

follow the change from: https://github.com/apache/nuttx/pull/930

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-27 12:35:04 +03:00
chao an
0eae218b49 arm/chip/sdio/muxbus: comment all undefined symbols
comment all undefined symbols to avoid build break if CONFIG_SDIO_MUXBUS enabled

Signed-off-by: chao an <anchao@xiaomi.com>
2023-03-26 13:04:48 -03:00
Xiang Xiao
901cd599b1 arch: Remove MIN macro definition
use the definition from sys/param.h instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-03-22 17:26:37 -03:00
Gustavo Henrique Nihei
e205d790ee risc-v/espressif: Fix inconsistencies in IRQ interface documentation
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-17 16:51:52 -03:00
Tiago Medicci Serrano
7b807a8540 esp32-esp32c3/wifi: remove naming inconsistencies
* Remove the 'COEXISTENCE' suffix from Wi-Fi's STA + SoftAP mode.
Coexistence usually refers to Wi-Fi + BLE, instead of Wi-Fi's
operation mode;
* Remove commented debug code;
* Remove outdate function descriptions;
2023-03-16 19:07:25 +01:00
Gustavo Henrique Nihei
b864f37613 risc-v/espressif: Add Watchdog support on top of MWDT0
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-14 23:55:35 +01:00
Gustavo Henrique Nihei
81499fcdf2 risc-v/espressif: Add support for ESP32-H2
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-14 23:55:35 +01:00
Gustavo Henrique Nihei
c149e52791 risc-v/espressif: Add support for ESP32-C6
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-14 23:55:35 +01:00
Gustavo Henrique Nihei
17f7f6e86d risc-v: Add Espressif chip family support on top of esp-hal-3rdparty
Initially supporting ESP32-C3 chip, to be followed by other RISC-V-based
chips from Espressif.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-14 23:55:35 +01:00
zhangyuan21
12bb4f04f1 arch: fixed error in the calculation of nwords caused an out of bounds
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-03-13 16:12:11 +09:00
Zhihong Chen
8f74ce8ac4 boards:riscv:hpm6750evk2: revised README.txt to config toolchain
- use hpmicro GNU riscv32 toolchain

Signed-off-by: Zhihong Chen <zhihong.chen@hpmicro.com>
2023-03-09 07:56:00 +02:00
Zhihong Chen
698f5f3e80 arch/riscv/Toolchain: add riscv32-unknown-elf selection
- user can use menuconfig to select riscv64-unknown-elf or riscv32-unknown-elf

Signed-off-by: Zhihong Chen <zhihong.chen@hpmicro.com>
2023-03-09 07:56:00 +02:00
Gustavo Henrique Nihei
1f54c024da espressif: Fix download of IDFboot binaries
It was broken after #8759, which erroneously substituted with MCUboot

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-03-08 15:55:35 -03:00
Karel Kočí
62661600b2 treewide: add DOWNLOAD variable as unification of curl call
This is a followup to the commit
03b164f59c.
2023-03-08 17:05:05 +08:00
Jari Nippula
aeddec2ec5 clear i2c ints before the transfer starts
If transfer is restarted in irq handler the interrupts shall be
cleared before the start bit is set in control register. This is
to avoid ints being accidentally cleared before they are handled leading
to timeout error.
2023-03-02 22:25:56 +08:00
Jari Nippula
6ba906691a clear spi int before the transfer starts
In spi_irq handler the data is written into txfifo and transfer
is started before the TXDONE interrupt is cleared. If the bus/memory
access is in some cases delayed, the spi transfer may have been
finished already before the interrupt register is cleaned for the
transfer. This leads the early arrived interrupt to be just removed
and never handled, which would cause a timeout error.
This patch moves the clearing of the interrupt to the place before
the tx is started, so the interrupt is not missed in above cases.
2023-03-02 22:05:25 +08:00
Gustavo Henrique Nihei
e4d219ca06 risc-v/esp32c3: Remove erroneous interrupt disable
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-02-28 22:14:54 +02:00
Alan Carvalho de Assis
49a5f02fb1 esp32c3: Fix missing irq timer 2023-03-01 01:22:24 +08:00
Huang Qi
8a389a06e1 Don't download tarball if a local git repo found
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-02-27 23:55:23 +08:00
Xiang Xiao
2c5f653bfd Remove the tail spaces from all files except Documentation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-26 13:24:24 -08:00
lilei19
38f64f559d change strcpy to strlcpy
Signed-off-by: lilei19 <lilei19@xiaomi.com>
2023-02-24 12:15:40 +08:00
Alan Carvalho de Assis
119dabaf73 esp32c3: Fix WDT incorrect interrupt enable/disable 2023-02-23 21:57:15 +02:00
Xiang Xiao
8b4ecac6c2 libc: Move math library from libs/libc/math to libs/libm/libm
to prepare the support of other implementation e.g.:
https://github.com/JuliaMath/openlibm
https://gitlab.com/gtd-gmbh/libmcs

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-23 10:40:07 +02:00
Fotis Panagiotopoulos
85ceb7920e Typo fixes. 2023-02-17 11:17:11 -03:00
Eero Nurkkala
b9ba262fb7 risc-v/mpfs: add athena irq defines
Add the Athena cryptographic microprocessor irq defines.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2023-02-15 00:21:03 +08:00
chenwen@espressif.com
cfc9029c5d risc-v/esp32c6: Add ESP32-C6 basic support
1. Bring up OS kernel.
  2. Add interrupt support.
  3. Add system timer support.
  4. Add the ESP32-C6 devkit board.
  5. Add basic UART support for console.
  6. Add clock configuration.
  7. Add board reset support.
2023-02-10 17:38:41 -03:00
Zhihong Chen
d082af34f7 add hpmicro chip: hpm6750
Signed-off-by: Zhihong Chen <zhihong.chen@hpmicro.com>
2023-02-09 14:17:49 +08:00
Lucas Saavedra Vaz
14d95eb131 arch/risc-v/esp32c3: Add RTC interrupt support 2023-02-08 10:42:19 +08:00
Ville Juven
f4b82b6405 sched/addrenv: Remove up_addrenv_restore
The function is not relevant any longer, remove it. Also remove
save_addrenv_t, the parameter taken by up_addrenv_restore.

Implement addrenv_select() / addrenv_restore() to handle the temporary
instantiation of address environments, e.g. when a process is being
created.
2023-02-08 02:51:23 +08:00
Ville Juven
5713d85df0 group/group_addrenv: Move address environment from group -> tcb
Detach the address environment handling from the group structure to the
tcb. This is preparation to fix rare cases where the system (MMU) is left
without a valid page directory, e.g. when a process exits.
2023-02-08 02:51:23 +08:00
Nathan Hartman
5f9cb6faf4 drivers/serial: Fix docstrings on UART interrupt handlers 2023-02-07 04:41:36 +08:00
chao an
7625126c91 Remove the remain MIN/MAX like macro
Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-03 23:22:41 +08:00
Alan Carvalho de Assis
e710ae5daf esp32c3: reserve CPUINTs 5 and 8 for BLE 2023-02-03 12:24:11 +08:00
Alan Carvalho de Assis
c12a60cb5a esp32c3: Fix WiFi adapter to use WMAC instead of MAC_NMI 2023-02-03 12:24:11 +08:00
Alan Carvalho de Assis
e950e53df2 esp32c3: Always reserve CPU INT 0 and fix cpu init order
Co-author: Tiago Medicci <tiago.medicci@espressif.com>
Co-author: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-02-03 12:24:11 +08:00
Xiang Xiao
df102d1f06 Remove OK macro from the code base
let's use OK from sys/types.h instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-02 13:58:16 +01:00
chao an
4c8d244fae sched/getpid: replace syscall getpid/tid/ppid() to kernel version
NuttX kernel should not use the syscall functions, especially after
enabling CONFIG_SCHED_INSTRUMENTATION_SYSCALL, all system functions
will be traced to backend, which will impact system performance.

Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-02 10:33:01 +08:00
Gustavo Henrique Nihei
e6b204f438 nuttx: Use MIN/MAX definitions from "sys/param.h"
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-02-01 23:47:44 +08:00
Stuart Ianna
05c6d7c7b9 litex: Add PWM driver.
PWM driver for multiple peripherals supplied in gateware.

Only single channel frequency and duty cycle control is implemented. Pulse counting and multichannel features are not currently feasible.

Additions also include a new board configuration for arty-a7 which enables the PWM driver and example application.
2023-02-01 09:34:57 -03:00
Huang Qi
8b27d60bcd tools: Make zig available for arm/riscv/sim
Add essential compile flags to make zig available out of box.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-02-01 11:12:44 +08:00
Stuart Ianna
26ac5335e5 litex: Add GPIO driver.
GPIO driver with optional ISR support. Allows for multiple GPIO peripherals to be specified at an arbitrary addresses.
2023-02-01 11:02:03 +08:00
Xiang Xiao
9f027208d4 fs: Add model field to geometry and mtd_geometry_s
the model is very useful to track the device info

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-31 11:50:28 -03:00
yinshengkai
3f97a87162 tools: add separate flags parameter for COMPILE/COMPILEXX
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-01-31 13:42:33 +08:00
Huang Qi
570c7587c7 risc-v/Toolchain.defs: Correct indent 2023-01-31 11:19:47 +08:00
lilei19
1d8af7e105 add holder for mutex
Signed-off-by: lilei19 <lilei19@xiaomi.com>
2023-01-31 12:08:05 +09:00
Nathan Hartman
6b89b6f945 Remove executable permissions from source files
* arch/arm/src/sama5/sam_flexcom_spi.h,
  arch/risc-v/src/mpfs/mpfs_ihc_sbi.c,
  drivers/usbdev/adb.c,
  libs/libc/math/lib_scalbn.c,
  libs/libc/math/lib_scalbnf.c,
  net/ipfrag/Make.defs,
  net/ipfrag/ipfrag.c,
  net/ipfrag/ipfrag.h,
  net/ipfrag/ipv4_frag.c,
  net/ipfrag/ipv6_frag.c: Remove executable permission.
2023-01-30 20:34:51 -03:00
zhangyuan21
e6d2f0623a backtrace: use CURRENT_REGS when in interrupt context
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-01-29 02:48:00 -08:00
Ville Juven
42d0e356c2 arch/addrenv: Change group_addrenv_t to arch_addrenv_t
This is preparation for moving address environments out of the group
structure into the tcb.

Why move ? Because the group is destroyed very early in the exit phase,
but the MMU mappings are needed until the context switch to the next
process is complete. Otherwise the MMU will lose its mappings and the
system will crash.
2023-01-27 23:17:01 +08:00
Gustavo Henrique Nihei
80bbb0f24c esp32c3: Fix IRQ initialization, it was crashing on DEBUG_ASSERTIONS
Co-author: Alan C. Assis <alan.carvalho@espressif.com>
2023-01-27 13:15:39 +08:00
chao an
931a4f6969 arch/EXTRA_LIBS: link all staging library
Signed-off-by: chao an <anchao@xiaomi.com>
2023-01-27 01:08:26 +02:00
Ville Juven
686b990a85 arch/ARCH_KERNEL_STACK: Fix signal handling with kernel stack
There were two issues with signal handling:
- With a kernel stack the "info" parameter was passed from kernel memory.
  This is fixed by making a stack frame to the user stack and copying it
  there.
- If the signal handler uses a system call, the kernel stack was completely
  and unconditionally destroyed, resulting in a crash in the user application

There is also no need to check ustkptr, it is always NULL. Why ? Because
signal delivery is deferred when a system call is being executed.
2023-01-26 20:41:42 +08:00
Petro Karashchenko
f952b8456c assert: switch from ASSERT(0/false) to PANIC
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-26 10:15:34 +08:00
Stuart Ianna
34fdc3da0d litex: Allow custom peripheral memory mapping and IRQ. 2023-01-25 14:11:06 +08:00
Ville Juven
9b88f8ea5c riscv/riscv_exception.c: Print the EPC value always
The value printed by assert() cannot always be trusted to be correct,
as it relies on the stack / stack pointer not being corrupt.

The CPU register always points to the faulting instruction so print it
out in the exception handler.
2023-01-25 00:55:07 +08:00
Stuart Ianna
f49c20d28f litex: System clock frequency selectable from Kconfig. 2023-01-24 08:20:16 +01:00
Gustavo Henrique Nihei
e77e12e145 espressif: Stabilize MCUboot support on Espressif chips
MCUboot support is no longer behind EXPERIMENTAL for the following
chips:
- ESP32
- ESP32-S2
- ESP32-S3
- ESP32-C3

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-01-24 08:44:22 +09:00
Jukka Laitinen
e2a7cee5ed arch/mpfs: Make selection of SBI boot or direct boot run-time configurable
Allow bootloader to select run-time whether the payload binary is booted with
SBI or directly by jumping to entrypoint address.

- Use just one bitmask to select sbi or direct boot for each hart
- Add mpfs_set_use_sbi function to allow selecting how to boot
- Initialize the bitmask by default according to the configuration flags
- Add a header file for including the function prototypes in bootloader code

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-01-20 00:08:51 +08:00
Xiang Xiao
fd64e38072 build: Add STACK_USAGE(-fstack-usage) to assist the stack analysis
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-19 10:35:20 -03:00
Masayuki Ishikawa
dc454765fb Revert "add holder for mutex"
This reverts commit fc176addeb.
2023-01-19 06:04:48 +09:00
Ville Juven
0922121bc0 riscv/addrenv: Do not free physical memory for SHM area
SHM area is just mapped memory, the physical backup is not owned by the
process, so the process must not free it.

In ARM this is already handled as the regions are destroyed one by one,
while this implementation does a page directory walk instead.
2023-01-18 21:59:55 +08:00
lilei19
fc176addeb add holder for mutex
Signed-off-by: lilei19 <lilei19@xiaomi.com>
2023-01-18 17:40:58 +08:00
Ville Juven
58b5a0412e riscv/addrenv_shm: Add missing sanity check to up_shmdt()
A missing sanity check, make sure the last level page table actually exists
before trying to clear entries from it.
2023-01-18 02:45:04 +08:00
Xiang Xiao
f64da13e9b libxx: Add CXX_STANDARD to select -std=c++??
and default to "c++17"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-16 15:41:57 +02:00
Jukka Laitinen
70de321de3 arch/Kconfig: remove virtual memory allocator dependency from MM_SHM
The dependency should be vice versa; the MM_SHM should depend on the
existence of the virtual memory range allocator.

Create a new CONFIG flag CONFIG_ARCH_VMA_MAPPING, which will define that
there is a virtual memory range allocator. Make MM_SHM select that flag

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2023-01-13 02:20:13 +08:00
chao an
eef818e51f risc-v/esp32c3: correct receive buffer size
1. correct receive buffer size, d_len should keep the l2 header size
2. fix race condition issue of de/enqueue rx queue

Signed-off-by: chao an <anchao@xiaomi.com>
2023-01-10 11:28:06 -03:00
anjiahao
c02fea36d8 arch:change tcbinfo regs num
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-01-05 23:36:12 +08:00
Xiang Xiao
779a610ca3 Remove the unnecessary NULL fields in global instance definition of file_operations
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-01-04 00:32:13 +02:00
Xiang Xiao
d3872e0479 arch/esp32c3: Fix the compiler error in esp32c3_spi.c
which is made by:
commit 87a1f69a3c
Author: Alan Carvalho de Assis <acassis@gmail.com>
Date:   Fri Dec 16 15:23:39 2022 -0300

    Modify the IRQ APIs to be compatible with ESP32/S2/S3

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-12-31 14:57:47 +02:00
Alan Carvalho de Assis
87a1f69a3c Modify the IRQ APIs to be compatible with ESP32/S2/S3 2022-12-31 12:47:41 +08:00
Alan Carvalho de Assis
1b58542dd4 esp32c3: Clear the timer interrupt to avoid losing the next one 2022-12-28 09:45:29 +08:00
Xiang Xiao
b9d7d00943 arch: Remove the unused arch color function variant
up_check_tcbstack_remain, up_check_stack, up_check_stack_remain and up_check_intstack_remain

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-12-24 22:40:52 +02:00
Masayuki Ishikawa
2f80a05eae arch: qemu-rv: Fix qemu_rv_mtimer_interrupt() for BUILD_KERNEL
Summary:
- I noticed that rv-virt:ksmp64 sometimes stops during boot.
- Finally, I found that it posts the Supervisor Software Interrupt
  before the OS finishes hardware initialization.
- This commit fixes this issue.

Impact:
- None

Testing:
- Tested with QEMU-7.1

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-12-24 11:25:39 -03:00
zhangyuan21
45394eb6dc arch: save user context in assert common code
This is the work continue with #7875

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2022-12-24 13:02:56 +08:00
Ville Juven
5fb3a960f5 riscv/addrenv: Test that satp contents make sense
Check that satp (the page directory root) is not 0, which means it has
not been set.
2022-12-23 10:47:04 +08:00
Petro Karashchenko
b107e4f417 nuttx: unify MIN, MAX and ABS macro definition across the code
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-12-21 09:31:28 +08:00
Xiang Xiao
fd0d6a9bf5 compiler.h: Add _ between format|printf|syslog|scanf|strftime and like
align with other macro naming style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-12-21 01:05:19 +02:00
Xiang Xiao
d5689e070b net/arp: Remove nuttx/net/arp.h
1.move ARPHRD_ETHER to netinet/arp.h
1.move arp_entry_s to net/arp/arp.h
2.move arp_input to nuttx/net/netdev.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-12-16 22:10:59 +02:00
zhangyuan21
453a1a7332 arch: move stack and task dump to common code
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2022-12-17 01:59:35 +08:00
Gustavo Henrique Nihei
7114cc2978 risc-v/esp32c3: Revert aes_cypher name change introduced in #6920
"aes_cypher" is a function from NuttX crypto, so better use instead of
defining a new interface in the driver.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-12-16 16:19:47 +02:00
zhangyuan21
632d87ee71 arch: remove up_release_pending function
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2022-12-16 21:29:57 +08:00
Lucas Saavedra Vaz
077c790830 arch: Make REG_[GET/SET]_FIELD thread safe for ESP SOCs 2022-12-16 13:32:43 +08:00
anjiahao
bc0fe0ea16 crypto:add some hardware support
esp32c3: aes hmac-sha1 hmac-sha256
stm32f0l0g0 stm32l1 : aes
sam34: aes
lpc43: aes
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2022-12-14 02:33:56 +08:00
chao an
47fbfa215e fs/hostfs: mode_t of mkdir(2) should use the nuttx prototype
Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-13 18:16:20 +08:00
田昕
0382b63f5d move common assert logic together.
Signed-off-by: 田昕 <tianxin7@xiaomi.com>
2022-12-12 17:05:02 +08:00
chao an
61563d6004 risc-v/es32c3: improve passthrough performance by iob offload
Use iob offload model to improve passthrough performance

1. Use iob buffer instead of reserved packet buffer
2. Enable TCP/UDP buffer mode

-------------------------------------------------
|  Protocol      | Server | Client |            |
|-----------------------------------------------|
|  TCP           |    7   |    12  |  Mbits/sec |
|  TCP(Offload)  |   17   |    11  |  Mbits/sec |
|  UDP           |   10   |    16  |  Mbits/sec |
|  UDP(Offload)  |   43   |    28  |  Mbits/sec |
-------------------------------------------------

Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-11 16:19:20 +08:00
Gustavo Henrique Nihei
9af5dca7dc risc-v/esp32c3: Refactor and rename linker scripts
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-12-09 11:19:27 +08:00
chao an
af149b44cd risc-v/backtrace: fix compile warning
common/riscv_backtrace.c: In function 'up_backtrace':
common/riscv_backtrace.c:145:27: error: passing argument 1 of 'backtrace' from incompatible pointer type [-Werror=incompatible-pointer-types]
  145 |           ret = backtrace(g_intstackalloc,
      |                           ^~~~~~~~~~~~~~~
      |                           |
      |                           uint8_t * {aka unsigned char *}
common/riscv_backtrace.c:64:33: note: expected 'uintptr_t *' {aka 'unsigned int *'} but argument is of type 'uint8_t *' {aka 'unsigned char *'}
   64 | static int backtrace(uintptr_t *base, uintptr_t *limit,
      |                      ~~~~~~~~~~~^~~~
common/riscv_backtrace.c:146:43: error: passing argument 2 of 'backtrace' from incompatible pointer type [-Werror=incompatible-pointer-types]
  146 |                           g_intstackalloc + CONFIG_ARCH_INTERRUPTSTACK,
      |                                           ^
      |                                           |
      |                                           uint8_t * {aka unsigned char *}
common/riscv_backtrace.c:64:50: note: expected 'uintptr_t *' {aka 'unsigned int *'} but argument is of type 'uint8_t *' {aka 'unsigned char *'}
   64 | static int backtrace(uintptr_t *base, uintptr_t *limit,
      |                                       ~~~~~~~~~~~^~~~~

Regression by:
| commit 70290b6e38
| Author: Xiang Xiao <xiaoxiang@xiaomi.com>
| Date:   Tue Sep 20 02:38:54 2022 +0800
|
|     arch: Change the linker generated symbols from uint32_t to uint8_t *
|
|     and remove the duplicated declaration
|
|     Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-07 19:13:09 +08:00
Xiang Xiao
c6e9edcbb6 net: Rename arp_arpin to arp_input
align with other similar function(e.g. ipv4_input and ipv6_input)

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-12-04 20:39:21 +08:00
Masayuki Ishikawa
3b2685409a arch: risc-v: Fix nsec overflow in riscv_mtimer_current()
Summary:
- I noticed that mtimer stops around 30min after boot.
- Finally, I found that nesc overflows in riscv_mtimer_current().
- This commit fixes this issue.

Impact:
- None

Testing:
- Tested with rv-virt:nsh on QEMU-7.1

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-12-01 19:33:39 +08:00
Masayuki Ishikawa
8053931d31 arch: qemu-rv: Add qemu_rv_virtio.c
Summary:
- This commit adds qemu_rv_virtio.c

Impact:
- None

Testing
- Tested with rv-virt:netnsh (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-11-29 13:16:44 +08:00
Xiang Xiao
6d30726a1b Remove the unnecessary "return;" at the end of function
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-11-27 22:23:50 +01:00
chao an
6fa60627eb net/devif/ip: build l2 header on the IP layer
Signed-off-by: chao an <anchao@xiaomi.com>
2022-11-27 12:13:45 +08:00
chao an
8850dee746 net/devif: move preprocess of txpoll into common code
Signed-off-by: chao an <anchao@xiaomi.com>
2022-11-27 12:11:12 +08:00
Alan Carvalho de Assis
0e57e69b08 Add libc_stubs functions to get hmac_md5()
Co-author: Gustavo Nihei <gustavo.nihei@espressif.com>
Co-author: Lucas Vaz <lucas.vaz@espressif.com>
2022-11-25 10:26:37 +08:00
田昕
28739b8b8a libc/stream:Add mtd backend stream.
Signed-off-by: 田昕 <tianxin7@xiaomi.com>
2022-11-24 12:07:10 +08:00
zhangyuan21
d8051ba979 nuttx/sched: merge up_block_task and up_unblock_task 2022-11-22 22:59:08 +08:00
zhangyuan21
a8fa51e6bf arch: rename arch special function name 2022-11-22 16:27:56 +08:00
zhangyuan21
5c1b518314 nuttx/sched: move reprioritize process to public function 2022-11-22 15:29:00 +09:00
zhangyuan21
08f7152d9f nuttx/sched: remove nxsched_remove_readytorun from up_block_task
It takes about 10 cycles to obtain the task list according to the task
status. In most cases, we know the task status, so we can directly
add the task from the specified task list to reduce time consuming.
2022-11-22 15:29:00 +09:00
zhangyuan21
e54b602208 nuttx/sched: remove nxsched_remove_blocked from up_unblock_task
It takes about 10 cycles to obtain the task list according to the task
status. In most cases, we know the task status, so we can directly
delete the task from the specified task list to reduce time consuming.
2022-11-22 15:29:00 +09:00
Eero Nurkkala
6596f0e99a risc-v/mpfs: fix compile warning
After commit b7d2b38, the system suffers from -Warray-bounds warning with -Wall:

chip/mpfs_opensbi.c: In function 'mpfs_hart_to_scratch':
chip/mpfs_opensbi.c:251:26: warning: array subscript hartid is outside array bounds of 'sbi_scratch_holder_t[0]' {aka 'struct sbi_scratch_holder_s[]'} [-Warray-bounds]
  251 |   return (unsigned long)(&g_scratches[hartid].scratch);

Fix it by reverting back to what is was earlier. g_scratches shouldn't be in the bss
region that would be zeroed out.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-11-21 14:43:34 +01:00
flyingfish89
f420b4dce7 esp32c3:fix i2c bug of timout
Signed-off-by: flyingfish89 <2914061332@qq.com>
2022-11-21 12:02:21 +01:00
Ville Juven
596ce5e7b1 riscv/addrenv: Implement up_shmat/shmdt for RISC-V
These are great utility functions to create/destroy anonymous mappings
2022-11-17 09:16:54 +08:00
Ville Juven
5c29042ab4 riscv/mmu: Implement mmu_ln_clear
Implement procedure to clear a mapping from MMU
2022-11-17 09:16:54 +08:00
Ville Juven
85470adcc3 riscv/addrenv: Make private function get_pgtable into a public one
The utility function can be used from other places
2022-11-17 09:16:54 +08:00
Ville Juven
093760b48c mpfs_head.S: Mark .start section attributes explicitly
a = allocated, x = executable. Otherwise the input section type will
become empty, which means output section will be empty as well.
2022-11-16 23:32:51 +08:00
Xiang Xiao
e244720aa4 bl602/spi: add reference in bl602_spibus_initialize
and unlock the mutex before return

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-11-14 09:34:04 +09:00
Xiang Xiao
14c3bc3b8c arch: Replace sem_t with mutex_t for the lock case
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

temp

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-11-14 09:34:04 +09:00
anjiahao
a4563b8744 Fix the coding style and typo issue
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-11-14 09:34:04 +09:00
anjiahao
d07792a343 Initialize global mutext/sem by NXMUTEX_INITIALIZER and SEM_INITIALIZER
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-11-14 09:34:04 +09:00
Eero Nurkkala
b7d2b38700 risc-v/mpfs: opensbi: fix random boot failures
After the commit b8b541f, the system would not start up properly
with certain coldboot conditions. For example, if the OpenSBI picked
hart4 as the coldboot hart in preference to hart3, the system would
get stuck due to stack corruption. OpenSBI uses a lottery mechanism
to pick the coldboot hart.

Also fix g_scratches area in such a manner than it will not get
initialized to zero. If several harts initialize the area to zero, there's
danger the stack pointer gets wiped out.

Now any coldboot hart works.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-11-05 00:37:51 +08:00
Ville Juven
e239cd942e mpfs/mpfs_mm_init: Fix the section align mask checks
The boundary-1 mask needs to be tested, not the alignment boundary
2022-11-04 23:03:10 +08:00
yinshengkai
85f727f232 tools: replace INCDIR to Makefile variable
In the past, header file paths were generated by the incdir command
Now they are generated by concatenating environment variables

In this way, when executing makefile, no shell command will be executed,
it will improve the speed of executing makfile
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2022-11-03 19:59:55 +08:00
Eero Nurkkala
3afc83abc7 risc-v/mpfs: ihc: reorganize ihc
Currently the IHC (Inter Hart Communication) depends on OpenAMP and
rptun.  However, the bootloader portion of the IHC doesn't need
either of them.  Now they are wasting a lot of bootloader space.

Reorganize the bootloader portion into a separate file 'mpfs_ihc_sbi.c'.
This file contains the OpenSBI vendor extensions, or the only required
functionalities for the bootloader.  On the other hand, 'mpfs_ihc.c'
contains the non-bootloader code.

This patch also makes it possible to utilize 2 RPMSG channels.  This
has been tested so that 2 separate NuttXs on harts 1 and 2 communicate
with Linux kernel that runs on harts 3 and 4.

New configuration files are added as well:
  - rpmsg-ch1:  sample config for RPMSG
  - rpmsg-ch2:  sample config for another RPMSG channel
  - rpmsg-sbi:  sample bootloader config for RPMSG/OpenSBI

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-11-02 21:44:52 +08:00
Eero Nurkkala
e50db35dc4 Revert "mpfs/mpfs_ddr.c: Stop the DDR training once it is completed"
This reverts commit ea9144bda8.

The commit made Icicle MPFS DDR useless. Revert the change for now.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-11-02 21:44:52 +08:00
Gustavo Henrique Nihei
f5c77933cb arch: Fix linking of multiple preprocessed linker script files
Only the last item from the ARCHSCRIPT list was being suffixed with
".tmp".

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-11-02 09:15:27 +08:00
Xiang Xiao
b607f80cf3 arch: Remove the unnecessary nosanitize_address from backtrace source code
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-29 08:26:04 +02:00
Jukka Laitinen
b2e239784f arch/risc-v/src/mpfs/hardware/mpfs250t_484_pinmap.h: Lower the default drive strength for MSSIO GPIOS
The default drive strength was way too high for normal GPIO usage, causing overshoots & clitches

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-10-28 22:42:17 +08:00
Jukka Laitinen
67a60d77dd arch/risc-v/src/mpfs: Add a configuration flag for SD-card card detect line
Make existence of the card detect line configurable

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-10-28 22:42:05 +08:00
anjiahao
2156a102cf fix bl602 i2c sem init mistake
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2022-10-27 21:21:01 +08:00
Gustavo Henrique Nihei
facdd4f2b9 esp32[-s2/-s3/-c3]: Re-sort SPI Flash configs
- Reduce "SPI Flash configuration" menu dependency on SPI Flash driver
  just to MTD-related configs.
- Move SPI Flash Mode and Frequency configs to SPI Flash configuration
  menu.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-10-27 10:07:40 +08:00
Petro Karashchenko
a74dddd2ff arch/risc-v/src/mpfs/hardware: fix alignment in comment
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-10-24 12:59:24 +08:00
anjiahao
e1ca516488 use SEM_INITIALIZER inside of NXSEM_INITIALIZER
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2022-10-22 14:50:48 +08:00
anjiahao
5724c6b2e4 sem:remove sem default protocl
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2022-10-22 14:50:48 +08:00
Xiang Xiao
774648de0f risc0v/bl602: Call kthread_create instead of nxtask_create in bl_os_task_create
since the kernel component should use the kernel thread instead the normal task

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-19 08:22:56 +09:00
Xiang Xiao
6b31918b42 Remove the unnecessary cast for main_t, NULL and argv
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-18 08:51:45 +02:00
anjiahao
dee38ce3e8 arch: Replace critical section with nxmutex in i2c/spi/1wire initialization
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-17 15:59:46 +09:00
anjiahao
d1d46335df Replace nxsem API when used as a lock with nxmutex API
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-17 15:59:46 +09:00
Brennan Ashton
4ce8cf7bdc bl602/dma: Fix possible call of null pointer to function 2022-10-11 14:34:52 +08:00
Jukka Laitinen
e793207bb6 arch/risc-v/src/mpfs: Add a config option for enabling L2 cache
Make a separate config flag for enabling L2 cache. This is on by
default when compiling a standalone/bootloader configuration, but
can also be disabled for special cases, such as memory testing

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-10-11 00:59:48 +08:00
Brennan Ashton
8b7d2d3da4 bl602: Fix bug in lli functionality for dma. 2022-10-09 12:06:15 +02:00
Masayuki Ishikawa
cb73e9a67d arch: qemu-rv: Refactor the entry point name for BUILD_KERNEL
Summary:
- This commit refactors the entry point name for BUILD_KERNEL
  to avoid misunderstanding the name

Impact:
- None

Testing:
- Tested with rv-virt:ksmp64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-09 14:08:47 +08:00
Masayuki Ishikawa
4b6c9915fe arch: qemu-rv: Fix timer and IPI handling for BUILD_KERNEL+SMP
Summary:
- I noticed that the OS timer sometimes proceeds fast when
  a task is scheduled to run on CPUO via IPI.
- Actually, qemu-rv implementation shares supervisor software
  interrupt for both timer and IPI on CPU0.
- This commit fixes this issue.

Impact:
- qemu-rv only

Testing:
- Tested with qemu-6.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-08 17:19:51 +08:00
Masayuki Ishikawa
4e095d2e90 arch: risc-v: Add SMP support for BUILD_KERNEL
Summary:
- This commit adds SMP support for BUILD_KERNEL

Impact:
- RISC-V: BUILD_KERNEL + SMP only

Testing:
- Tested with rv-virt:ksmp64 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-08 09:25:41 +08:00
Ville Juven
0d52b5be56 mpfs_mm_init: Mark the L2 kernel page table as a global mapping
Kernel mappings are global, i.e. they exist in every address environment
2022-10-07 17:26:21 +08:00
Ville Juven
373568f63a mpfs_mm_init.c: Ensure the L3 page table size is large enough
Run-time check for L3 page table size, to ensure it is large enough
to map all of the kernel memory.

NOTE: The check has to be run-time, as KFLASH_SIZE/KSRAM_SIZE are really
linker relocation symbols, and thus cannot be utilized compile-time.
2022-10-07 17:26:21 +08:00
Ville Juven
dbc9a5ffa2 riscv_mmu: Add some basic sanity checks for section boundaries
L3 table maps 2MB of memory, this brings an implicit requirement for
any L3 region to be aligned to 2MB. This commit adds build time sanity
checks to ensure this requirement is met.

For other SvXX architectures the boundary requirement (might be) is
different.
2022-10-07 17:26:21 +08:00
Masayuki Ishikawa
df6bf3e614 arch: risc-v: Introduce RISCV_IPI macro for SMP
Summary:
- This commit introduces RISCV_IPI macro for SMP
- Also, replace RISCV_IRQ_MSOFT with RISCV_IRQ_SOFT
- Remove duplicate irq_attach() from qemu_rv_irq.c

Impact:
- None

Testing:
- Tested with rv-virt:smp64 and maix-bit:smp on QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-07 14:49:29 +08:00
Masayuki Ishikawa
a7bca63b3b arch: qemu-rv: Fix build errors in chip.h for BUILD_KERNEL + SMP
Summary:
- This commit fixes build errors for BUILD_KERNEL + SMP

Impact:
- None

Testing:
- Tested with rv-virt:ksmp64 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-05 17:19:13 +08:00
Masayuki Ishikawa
c4901d6f4b arch: risc-v: Introduce g_percpu_spin in riscv_percpu.c
Summary:
- This commit introduces g_percpu_spin to avoid deadlock
  in riscv_percpu.c instead of using the global spinlock.

Impact:
- None

Testing:
- Tested with rv-virt:knsh64 and rv-virt:ksmp64 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-05 05:15:38 +02:00
Brennan Ashton
102c63be9e bl602: Add initial DMA support, including SPI over DMA. 2022-10-03 16:01:30 -03:00
Jukka Laitinen
03bce705d5 arch/risc-v/src/mpfs/mpfs_ethernet.c: Set PHY speed advert after PHY reset
This allows properly using 10/100Mbps also with 1G phy. Some gigabit PHYs
come out of reset with 1G advertisement enabled, causing other devices to
set up link with 1G. If, after this, the link is set to 10/100 on the mpfs,
the link won't work.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-10-03 19:35:30 +02:00
Masayuki Ishikawa
2fa872e304 arch: qemu-rv: Add M-timer handling for BUILD_KERNEL
Summary:
- In RISC-V, BUILD_KERNEL uses S-mode and to use M-mode timer
  we need to handle it by using OpenSBI or self-implementation.
- This commit adds M-timer self-implementation for BUILD_KERNEL.

Impact:
- qemu-rv only

Testing:
- Tested with rv-virt:knsh64 on qemu-6.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-03 23:26:11 +08:00
Masayuki Ishikawa
b3e300f8e6 arch: qemu-rv: Fix qemu_rv_start_s() for S-mode
Summary:
- I found inappropriate SET_CSR() usage in the function.
- This PR fixes this issue.

Impact:
- None

Testing:
- tested with rv-virt:knsh64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-10-02 22:32:07 +08:00
Xiang Xiao
e38248ee08 Return -EINVAL for the internal API
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-30 17:54:56 +02:00
Xiang Xiao
bdeaea3742 Remove the unnessary empty line after label
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-30 17:54:56 +02:00
Gustavo Henrique Nihei
c0cd56a758 risc-v/esp32c3: Fix retrieval for linker-defined symbol
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-09-29 23:31:48 +02:00
chao an
6bc4baa4ca arch/makefile: preprocess link script to make configure more flexibly
Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-29 17:06:47 +08:00
yinshengkai
5c9b094d65 tools: Replace mkallsyms.sh with mkallsyms.py
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2022-09-29 08:33:04 +08:00
Jukka Laitinen
24ea8ee3e9 arch/risc-v/src/mpfs/mpfs_ddr.c: Use DDR type selection macros to flag out code
The DDR type can be determined at compile time, remove code which is not used

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-09-28 02:09:02 +08:00
Jukka Laitinen
0ba3bc66be arch/risc-v/src/mpfs/Kconfig: Add configuration flags for DDR type selection
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-09-28 02:09:02 +08:00
Masayuki Ishikawa
0cd896b1d5 arch: risc-v: Fix license information to use the OpenSBI
Summary:
- I noticed that the OpenSBI library depends on the BSD license
- This commit fixes this issue

Impact:
- CONFIG_OPENSBI=y only

Testing:
- Build with icicle:opensbi (will be updated later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-09-27 18:29:09 +02:00
Xiang Xiao
40ef5bc6db libc: Move queue.h from include to include/nuttx
to avoid the conflict with libuv's queue.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-26 08:04:58 +02:00
Xiang Xiao
70290b6e38 arch: Change the linker generated symbols from uint32_t to uint8_t *
and remove the duplicated declaration

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-24 21:26:56 +02:00
Xiang Xiao
3c1c29f2c4 arch: move non arm g_current_regs defintion to common place
to avoid the code duplicaiton

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-21 22:23:11 +02:00
Masayuki Ishikawa
a2deaa73c3 arch: risc-v: Remove FPU support from qemu-rv
Summary:
- Because a context switch issue still exists with FPU
  the configs should be removed until it works.

Impact:
- None

Testing:
- Tested with ostest

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-09-20 11:40:40 +08:00
Xiang Xiao
8a265e274d Kconfig: Remove EXPERIMENTAL for features which is been around a long time
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-19 11:39:22 -03:00
chao an
f23a736c80 nxstyle: correct the file path
Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-18 01:35:21 +08:00
teknokita
1adef79c24 add include <nuttx/fs/ioctl.h> to esp32c3_usbserial.c
undeclare TCGETS on esp32c3 when enable usbserial and termios
error:
chip/esp32c3_usbserial.c: In function 'esp32c3_ioctl':
chip/esp32c3_usbserial.c:411:10: error: 'TCGETS' undeclared (first use in this function)
2022-09-17 17:06:58 +08:00
ligd
e2df52390a SMP: fix crash when switch to new task which is still running
Situation:

Assume we have 2 cpus, and busy run task0.

CPU0                                CPU1
task0 -> task1                      task2 -> task0
1. remove task0 form runninglist
2. take task1 as new tcb
3. add task0 to blocklist
4. clear spinlock
                                    4.1 remove task2 form runninglist
                                    4.2 take task0 as new tcb
                                    4.3 add task2 to blocklist
                                    4.4 use svc ISR swith to task0
                                    4.5 crash
5. use svc ISR swith to task1

Fix:
Move clear spinlock to the end of svc ISR

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-17 17:37:47 +09:00
Xiang Xiao
a7b3217c37 boards/arch: Remove FAR from 32bit/64bit arch
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-16 10:22:12 +02:00
Eero Nurkkala
ec026c14cb risc-v/mpfs: emmcsd: further enhance the clocking
Simplify the clock mode from the board.h -files. Also make the
SD clock definable as well.

Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-09-15 01:55:33 +08:00
Ville Juven
ea9144bda8 mpfs/mpfs_ddr.c: Stop the DDR training once it is completed
The DDR training IP stays active otherwise, so stop it when the training
is complete.

This fixes a potential interrupt storm via MPFS_IRQ_DDRC_TRAIN.
2022-09-14 22:31:36 +08:00
Eero Nurkkala
e5305a250a risc-v/mpfs: emmcsd: provide options for selecting clk speed
Some related products, such as Aries m100pfs, don't support eMMC
speeds up to 200MHz. Thus, provide option to select slower clock.
This has only to do with the clocking, no CMD6 is sent to select
high speed modes.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-09-13 11:23:45 +08:00
Ville Juven
ff05cc593f risc-v/mmu: Fix L3 mappings for kernel, and mpfs protected mode userspace
The L3 mapping function was just way too simplistic. Depending on memory
configuration it either works or not.

Noticed that with icicle:pnsh the software crashes due to instruction
page fault, reason is the map_region() implementation that does not
work for regions that are not aligned to 2MB (the L2 page size).

Implemented an extremely simplistic page table allocator for the L3
references, that should once and for all get rid of the L3 mapping issue.

NOTE: gran_alloc() cannot be used at this point, it is too early for it.
2022-09-12 18:01:08 +09:00
ligd
b3ebe66ff5 arch: dump backtrace should after set rtcb regs
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-10 12:48:11 +08:00
ligd
a3f9bd3786 backtrace: fix busy loop backtrace
Situation:
1. user call assert
2. crash in assert
3. crash happend, do backtrace
4. backtrace interrupt stack successful
5. busy loop backtrace user stack with CURRENT_REGS

Fix:
use rtcb->regs instead

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-09-10 12:48:11 +08:00
Eero Nurkkala
945e531eaf risc-v/mpfs: emmcsd: allow switching from SD to eMMC
If the system starts up using the SD-card, and later wants
to switch to use the eMMC, it's not going to happen. SD-card
will be kept selected within the FPGA making the transition
fail.

It's been possible to switch from eMMC to SD, but now the
transition is possible for both directions.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-09-09 21:40:35 +08:00
Eero Nurkkala
5cedf1ef2a risc-v/mpfs: usb: fix usb restart
Issuing the following commands doesn't succeed:
  - conn
  - disconn
  - conn
This USB driver doesn't even disconnect without this patch.

If the USB driver has been started from another hart, closing it
will not disable the PLIC interrupt. This means it's possible many
harts get the USB interrupt and thus make the USB look very unstable.

Fix these problems by disconnecting the USB via the USB_POWER
register at shutdown and disabling the interrupt at shutdown. Also
clear the software internals via the mpfs_sw_setup() for the conn /
disconect loop to succeed.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-09-08 22:08:17 +08:00
Eero Nurkkala
4df8b16060 risc-v/mpfs: usb: provide more endpoints
The underlying hardware supports 9 endpoints:
  - EP0
  - 4x IN EPs
  - 4x OUT EPs

Currently the driver assumes every EP number is unique. This limits
the amount of EPs to 1 + 4 = 5. Utilize the EPs in such a manner
that all may be used.

Also fix a few error handling related bugs. Update the composite
driver to match the current situation as well.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-09-06 23:10:30 +08:00
Gustavo Henrique Nihei
c5785ee9d5 risc-v/esp32c3: Fix some UBSAN shift-out-of-bounds warnings
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-09-03 00:29:02 +08:00
Huang Qi
32a21a1b67 UBSan: Allow custom the sanitizer in Kconfig
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-09-02 19:07:09 +08:00
wangbowen6
b15d38246c up_nputs: fix AddressSanitizer: global-buffer-overflow problem
==2117790==ERROR: AddressSanitizer: global-buffer-overflow on address 0x64d9e3c0 at pc 0x59ac4e16 bp 0xcefe8058 sp 0xcefe8048
READ of size 1 at 0x64d9e3c0 thread T0
    #0 0x59ac4e15 in up_nputs sim/up_nputs.c:54
    #1 0x59a67e4c in syslog_default_write syslog/syslog_channel.c:220
    #2 0x59a67823 in syslog_default_write syslog/syslog_write.c:101
    #3 0x59a67f10 in syslog_write syslog/syslog_write.c:153
    #4 0x59a651c3 in syslogstream_flush syslog/syslog_stream.c:60
    #5 0x59a6564e in syslogstream_addchar syslog/syslog_stream.c:104
    #6 0x59a6576f in syslogstream_putc syslog/syslog_stream.c:140
    #7 0x5989fc4d in vsprintf_internal stdio/lib_libvsprintf.c:952
    #8 0x598a1298 in lib_vsprintf stdio/lib_libvsprintf.c:1379
    #9 0x59a64ea4 in nx_vsyslog syslog/vsyslog.c:223
    #10 0x598a601a in vsyslog syslog/lib_syslog.c:68
    #11 0x59b0e3dc in AIOTJS::logPrintf(int, char const*, ...) src/ajs_log.cpp:45
    #12 0x59b03d56 in jse_dump_obj src/jse/quickjs/jse_quickjs.cpp:569
    #13 0x59b03ea1 in jse_dump_error1(JSContext*, unsigned long long) src/jse/quickjs/jse_quickjs.cpp:602
    #14 0x59b03dd9 in jse_dump_error(JSContext*) src/jse/quickjs/jse_quickjs.cpp:591
    #15 0x59bed615 in ferry::DomComponent::callHook(char const*) src/framework/dom/component.cpp:65
    #16 0x59bfe0ff in ferry::DomComponent::initialize() src/framework/dom/component.cpp:645
    #17 0x59bb141d in dom_create_component(JSContext*, unsigned long long, unsigned long long, unsigned long long) (/home/wangbowen/project/central/vela_miot_bes_m0/bin/audio+0x365c41d)
    #18 0x59b4c0d3 in AIOTJS::__createComponent(JSContext*, unsigned long long, int, unsigned long long*) (/home/wangbowen/project/central/vela_miot_bes_m0/bin/audio+0x35f70d3)
    #19 0x5a56ec17 in js_call_c_function quickjs/quickjs.c:16108

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-09-01 11:51:48 +08:00
Masayuki Ishikawa
b7063427c8 arch: risc-v: Fix up_check_tcbstack() for CONFIG_ARCH_ADDRENV=y
Summary:
- I noticed that ps shows incorrect stack usage when running
  getprime in the background.
- With CONFIG_ARCH_ADDRENV=y, a user task including pthread
  allocates its stack in the user space that needs to be
  accessed with a correct address environment.
- This commit fixes this issue.

Impact:
- CONFIG_ARCH_ADDRENV=y only

Testing:
- Tested with rv-virt:knsh64 on qemu-6.2

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-08-31 09:20:36 +08:00
Masayuki Ishikawa
e2f0f431d9 arch: risc-v: Assign dedicated virtual addresses for text and heap
Summary:
- Current RISC-V/NuttX implementation assumes that text/data/heap
  areas are continuous. In fact, CONFIG_ARCH_TEXT_VBASE and
  CONFIG_ARCH_HEAP_VBASE are not used for memory allocation.
- This commit assigns dedicated virtual addresses for text and heap
  which are the same approach to ARM-v7A/NuttX implementation.

Impact:
- None

Testing:
- Tested with rv-virt:knsh64 (will be updated later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-08-30 22:52:01 +08:00
Huang Qi
f93964ad3c riscv: Dump trap val in exception handler
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-08-30 14:55:33 +08:00
Eero Nurkkala
3665180795 risc-v/mpfs: usb: fix cppcheck findings
Fix the following cppcheck findings. Privreq may be NULL,
thus perform checks before using its member variables.

Checking mpfs_usb.c ...
mpfs_usb.c:1093:12: warning: Possible null pointer dereference: privreq [nullPointer]
      if ((privreq->inflight > 0) && (count != 0) &&
           ^
mpfs_usb.c:1090:21: note: Assignment 'privreq=NULL', assigned value is 0
          privreq = NULL;
                    ^
mpfs_usb.c:1093:12: note: Null pointer dereference
      if ((privreq->inflight > 0) && (count != 0) &&
           ^
mpfs_usb.c:1138:3: warning: Possible null pointer dereference: privreq [nullPointer]
  privreq->req.xfrd = 0;
  ^
mpfs_usb.c:1130:21: note: Assignment 'privreq=NULL', assigned value is 0
          privreq = NULL;
                    ^
mpfs_usb.c:1138:3: note: Null pointer dereference
  privreq->req.xfrd = 0;
  ^
mpfs_usb.c:1139:3: warning: Possible null pointer dereference: privreq [nullPointer]
  privreq->inflight = privreq->req.len;
  ^
mpfs_usb.c:1130:21: note: Assignment 'privreq=NULL', assigned value is 0
          privreq = NULL;
                    ^
mpfs_usb.c:1139:3: note: Null pointer dereference
  privreq->inflight = privreq->req.len;
  ^
mpfs_usb.c:1140:50: warning: Possible null pointer dereference: privreq [nullPointer]
  priv->eplist[epno].descb[0]->addr = (uintptr_t)privreq->req.buf;
                                                 ^
mpfs_usb.c:1130:21: note: Assignment 'privreq=NULL', assigned value is 0
          privreq = NULL;
                    ^
mpfs_usb.c:1140:50: note: Null pointer dereference
  priv->eplist[epno].descb[0]->addr = (uintptr_t)privreq->req.buf;

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-08-30 01:41:28 +08:00
Eero Nurkkala
90d9b6b8ac risc-v/mpfs: usb: fix infinite loop issue
mpfs_write_tx_fifo() gets stuck in the following case:
  - CDCACM is used
  - ttyACM0 is opened and then closed from the remote end,
    such as Linux or Windows
  - data is written into ttyACM0 from NuttX
  - tx fifo will never get empty and the system is stuck

Fix this by issuing an error code if the transmit fifo doesn't
proceed as expected. The error code is then propagated into
higher level keeping the system functional.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-08-29 21:35:54 +08:00
Gustavo Henrique Nihei
5ed2ee85c9 arch: Improve documentation for up_fpucmp function
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-08-26 11:57:06 +08:00
Eero Nurkkala
71ace555f2 risc-v/mpfs: ihc: fix performance issue
nxsig_usleep() will wait for the next timer tick which is way
too much here. It's not sleeping 100 us, but rather, near 1/60 s.

This causes severe performance problems. Fix this by polling the
register for a while if the remote end is busy.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-08-26 02:12:26 +08:00
Huang Qi
e4e3208180 Replace all strncpy with strlcpy for safety
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-08-25 13:38:36 +08:00
Jukka Laitinen
c7a904fa12 arch/risc-v/src/mpfs: Fixes for MSSIO GPIO configurations
- Clarify the macros MSSIO_EC_DEFAULT and MSSIO_EC_USB_DEFAULT
- Remove PULLDOWN bit from MSSIO_EC_DEFAULT, it was on by accident
- Fix some EC configuration macros; DRVSTR was wrong, clean up the others
- Define GPIO_PULLUP and GPIO_PULLDOWN like on many other platforms

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-08-24 19:25:05 +08:00
Eero Nurkkala
d940d55ee4 risc-v/mpfs: ihc: update vq ids
Since the commit cf22dd8 (related to OpenAMP update), the notifyid
is no longer NOTIFY_ALL, but the vq id.

Utilize the vq id now properly as it's being provided. However,
vq id 0 generates action.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-08-24 02:35:00 +08:00
Xiang Xiao
c44a7cbf88 arch: Add ARCH_COVERAGE_ALL option
so the user could disable the full image instrumentation,
but enable the instrumentation by files or directories.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-08-23 17:50:52 +02:00
Xiang Xiao
f1355680ca mm/kasan: Add MM_KASAN_ALL option
so the user could disable the full image instrumentation,
but enable the instrumentation by files or directories.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-08-23 17:50:52 +02:00
Huang Qi
a06ec54cd0 debug: Introduce portion of UBSan
without UBSan
```
 text    data     bss     dec     hex filename
  85612     208  142258  228078   37aee nuttx
```

with UBSan:
```
   text    data     bss     dec     hex filename
 194290   98164  208634  501088   7a560 nuttx
```

```c
int main(int argc, FAR char *argv[])
{
  uint32_t ptr[32];
  printf("Hello, World!! %lu\n", ptr[64]);
  return 0;
}
```
Try to run this sample:
```
nsh> hello
ubsan_prologue: ================================================================================
ubsan_prologue: UBSAN: array-index-out-of-bounds in hello_main.c:39:37
__ubsan_handle_out_of_bounds: index 64 is out of range for type 'uint32_t [32]'
ubsan_epilogue: ================================================================================
Hello, World!! 1070182368
nsh>
```

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-08-22 13:57:29 +08:00
Ville Juven
75ba9001bc risc-v/mpfs: Make entrypoint table run-time configurable
Default values still come from configuration, but this gives the option
to modify the per-hart entrypoints.
2022-08-18 21:50:53 +08:00
Eero Nurkkala
a1ff841ca4 risc-v/mpfs: ihc: don't use semaphores with OpenSBI vendor calls
OpenSBI vendor extension calls must not cause scheduling, as they're
part of M-mode trap handling. Thus, comment out nxsig_usleep() as
well, which is occasionally taken and crashes the system in that
case. Fix this by commenting out lines that have the potential to
cause scheduling.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-08-17 18:33:32 +08:00
Masayuki Ishikawa
548540eb13 arch: qemu-rv: Fix high CPU usage in SMP mode
Summary:
- I noticed that QEMU shows high CPU usage if the number of
  CPUs does not match the kernel configuration. (e.g. -smp 8
  and CONFIG_SMP_NCPUS=2)
- This commit fixes this issue.

Impact:
- qemu-rv only

Testing:
- Tested with the following configs
  - rv-virt:smp64 (CONFIG_NCPUS=1/2/8)
  - rv-virt:nsh64

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-08-13 22:41:42 +03:00
Xiang Xiao
2b37909c9e libc: Move crc8.h, crc16.h and crc32.h from include to include/nuttx
to avoid the conflict with the 3rd party library

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-08-13 13:28:24 +03:00
Ville Juven
b8b541fbf5 mpfs: Remove the ddrstorage section from the OpenSBI package
It is not really needed; g_hart_stacks is only used during SBI init as
a temporary stack area. We can use the scratch area buffers for this, as
the scratch areas define almost 4K of extra space, which is used for
exception stacks anyway.
2022-08-10 10:01:47 +03:00
Ville Juven
60042fea74 risc-v: Implement riscv_sbi_set_timer
This implements riscv_sbi_set_timer. This requires the OpenSBI companion
software to work (but this is needed by the kernel mode anyways).
2022-08-10 02:02:39 +08:00
Ville Juven
31bb362aab risc-v: Fix kernel MMU mapping for L3 table
The L3 table address was calculated incorrectly. For every 2MiB of
mapped memory, an offset of 4KiB is needed from the base of the L3
table. The old calculation failed if paddr was not aligned to a 2MiB
boundary.
2022-08-09 23:14:46 +08:00
Petro Karashchenko
b3cd9090d1 drivers/net: make sure that net driver d_buf is 16-bit aligned
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-08-05 22:21:37 +08:00
Xiang Xiao
c61381da56 arch/risc-v: Fix error: invalid application of 'sizeof' to incomplete type 'struct tls_info_s'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-08-05 08:45:11 +03:00
Nathan Hartman
20bdd44e7b Remove executable permission from source and build files. 2022-08-04 12:48:18 -03:00
Eero Nurkkala
e0291b1ce8 risc-v/mpfs: usb: configure fifos properly
RX_FIFO_ADDRs and TX_FIFO_ADDR were misconfigured. These addresses
overlapped causing data corruption during high USB loads. For
example, data corruption was present during the following conditions:

  1. Composite USB driver was used (CDC/ACM + Mass storage)
  2. /dev/ttyACM0 was accessed instantly from Linux side when
     starting up.
  3. Training data was sent to /dev/ttyACM0 from NuttX from the
     very beginning periodically.

It was observed that while Mass storage was negotiating, sometimes
data sent from NuttX to Linux via CDC/ACM was corrupt, although it
was sent properly on the TX fifo.

Also, don't access TXCSRL_REG_EPN_TX_FIFO_NE_MASK for EP0 as it's
not applicable.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-08-03 23:44:12 +08:00
ligd
8c1fd1df81 rptun: update rptun to openamp 2022.04.0
Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-08-03 01:22:53 +08:00
zhuyanlin
031c89db89 power: add PM_IDLE_DOMAIN to pm.h and remove definations
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-07-29 11:15:40 +08:00
Xiang Xiao
13a7ae3d06 arch: Call board_reset before up_irq_save and spin_trylock
since board_reset may call some kernel functions which try
to acquire the lock again

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-28 08:18:24 -04:00
Masayuki Ishikawa
1742b7f6a4 arch: risc-v: Fix warnings in common/crt0.c
Summary:
- This commit fixes warnings in common/crt0.c

Impact:
- None

Testing:
- Build only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-07-27 23:22:23 +08:00
Jiuzhu Dong
9d4549d48b arch: limit output maximum size stackdump when sp is not within stack
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
Jiuzhu Dong
136b1d6d42 arch: using remain to ignore invalid stack content when sp is not within stack
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
Jiuzhu Dong
91d8ed319e arch/riscv: optimize stackdump
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
Jiuzhu Dong
5c8fd46126 arch/stack: rename do_stack_check with arch prefix
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
Jiuzhu Dong
79597d0caf arch/up_stack_check: using running_task to get correct task context
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
2022-07-27 20:48:33 +08:00
ligd
8a3683fb9f rptun: add ns_match callback to resolve rptun deadlock
thread A: accept -> net_lock -> socket_rpmsg_accept
          -> rpmsg_register_callabck -> rptun_lock
thread B: ns_bind -> rpmsg_socket_ns_bind -> get_tx_payload_buffer
          -> rptun_wait_tx -> usrsock_rpmsg_ept_cb -> usrsockdev_write
          -> net_lock -> deadlock

fix:
add ns_match callback

Signed-off-by: ligd <liguiding1@xiaomi.com>
2022-07-27 20:36:51 +08:00
Jouni Ukkonen
e268b23142 OpenSBI: Add configurable support for domain init
Initialize .domains_init function entry point in sbi_platform_operations when
CONFIG_OPENSBI_DOMAINS=y. In this case, the board specific code must provide
the "board_domains_init" function.

Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2022-07-22 19:00:33 +03:00
Abdelatif Guettouche
ae1cbc47ef esp32&c3/Kconfig: CONFIG_ESP32(C3)_WIRELESS doesn't need to be user
selectable.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-07-20 22:02:28 +03:00
Abdelatif Guettouche
20c6996e81 esp32c3/Kconfig: Don't select options already selected.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-07-20 22:02:28 +03:00
Xiang Xiao
2166c98809 Add printflike and scanflike to all printf/scanf like functions
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-18 14:14:36 +03:00
Xiang Xiao
aad5fbd2fb arch: Add up_nputs function to handle the non '\0' string correctly
and change up_puts as a simple macro

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-17 17:31:19 +03:00
Gustavo Henrique Nihei
e24621d545 arch: Convert DEBUGASSERT(false) into more intuitive DEBUGPANIC()
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-14 12:08:45 +08:00
Gustavo Henrique Nihei
8a4c9c3489 arch: Fix typo in "register" word
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-13 22:57:19 +03:00
Eero Nurkkala
14447600ac risc-v/mpfs: usb: fix illegal reads
With faster data transfer rates, it was seen that the read
requests occasionally were issued while the USB RX operation
was actually in progress.  This patch makes sure the system
doesn't accidentally read the RX fifo while it's being filled
up, but rather, checks for the RXCSRL_REG_EPN_RX_PKT_RDY_MASK
flag.  This flag indicates the packet is ready to be read.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-07-12 18:34:28 +08:00
Gustavo Henrique Nihei
5e32aa14bf risc-v/esp32c3: Fix verification of ROM function return values
cache_dbus_mmu_set and cache_ibus_mmu_set return positive values in case
of errors, so DEBUVERIFY could never detect them since this macro checks
for negative values.
Besides, the successful execution of those functions is mandatory for
the reliable operation under Protected Mode, so the verification is
always performed, even when DEBUG is not enabled.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-07-12 10:56:59 +08:00
Nathan Hartman
849f760b77 Fix various typos 2022-07-08 02:15:54 +08:00
Abdelatif Guettouche
0bdf713df0 risc-v/esp32c3: Add the rest of the reset causes.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-07-08 01:06:35 +08:00
Xiang Xiao
3daa18b661 arch: Remove the unnecessary #if/#endif in assert
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-07 19:25:47 +03:00
Xiang Xiao
9ff0971d3f arch: Correct the order of stack related information in assert
forget to update in this patch:
commit b02db04e00
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date:   Sun Jun 5 17:10:19 2022 +0800

    arch/assert: Keep the thread dump column order same as ps

    Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-07 19:25:47 +03:00
Xiang Xiao
9ab3417882 arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place
1.Move __XSTR from include/arch.h to include/irq.h
2.Move  FLOAD/FSTORE and REGLOAD/REGSTORE from include/arch.h to src/common/riscv_internal.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:25:56 +03:00
Xiang Xiao
c20ed58879 arch: Remove the inclusion of arch/irq.h from chip/irq.h
since arch/irq.h will include chip/irq.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-04 13:03:47 +03:00
Xiang Xiao
3d1ce144df arch: Move up_getsp from arch.h to irq.h
since all other special register operation in irq.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-07-01 10:44:55 -03:00
Gustavo Henrique Nihei
5ce77fad1b arch: Remove "0x" prefix preceding "%p" specifier on format string
The "p" format specifier already prepends the pointer address with "0x"
when printing.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-30 22:08:58 +03:00
Eero Nurkkala
ef28d915fe risc-v/mpfs: ihc: don't start rptun automatically
Starting the rptun with the autostart flag set will cause significant
delays at the boot, as it will wait for the master to be up. U-boot/linux
combination may take more than 10 seconds to boot to the point where the
rpmsg bus is initialized.

For now, the user needs to initialize the rptun separately, for example,
by issuing the following command:

  rptun start /dev/rptun/mpfs-ihc

This command will also block if started before the rpmsg bus master is up.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-28 11:34:38 -03:00
Ville Juven
cfebb5a5c1 risc-v: Move common memory map to its own file from riscv_internal
Move the linker defined symbols to a separate file, so they can be
accessed without pulling in everything from riscv_internal.h and
whatever it includes (e.g. syscall.h drags in a lot).
2022-06-28 14:41:56 +03:00
Nimish Telang
4afd25b567 this flag is meaningless for the linker 2022-06-27 20:03:03 -03:00
Ville Juven
77a01cfe52 mpfs: Fix IHC memory locations to native width type
Ne numeric type defaults to u32 which is not enough to represent a
native memory location

This fixes build error:
https://github.com/apache/incubator-nuttx/runs/7067877053?check_suite_focus=true
2022-06-27 20:49:00 +08:00
Jukka Laitinen
ba1b8d0712 arch/risc-v/src/mpfs: Add mpfs_gpiosetevent and gpio irq handling functions
Add a function to easily enable event handling on fabric and mss gpios. This
is similar to what exists e.g. for stm32 arm chips.

Also fix some small bugs in mpfs_configgpio related to IRQ bits configuration

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-06-23 21:45:15 +08:00
Eero Nurkkala
92760f89eb risc-v/mpfs: emmcsd: fix two issues
This patch fixes the following issues:
  1. MPFS_EMMCSD_HRS06_EMM bitmask had to be 0x7, not 0x03
  2. putreg32() caused outright memory corruption as the
     arguments were in wrong order

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-22 09:50:33 +03:00
Huang Qi
9481456fde risc-v/esp32c3: Implement up_perf_xxx API
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-06-21 21:35:22 +08:00
Richard Tucker
8f36649aad arch/risc-v/src/litex/litex_emac: add liteeth peripheral driver
See the following for details on the pepheral:
https://github.com/enjoy-digital/liteeth
2022-06-21 12:06:37 +03:00
AuroraRAS
0fe219a8c9 Add I2C_M_NOSTART and I2C_M_NOSTOP support in esp32c3_i2c
Signed-off-by: AuroraRAS <chplee@gmail.com>
2022-06-20 10:34:22 -03:00
Ville Juven
6cb77a8d84 mpfs: Allow mapping of RAM/ROM regions from different memory areas
The old implementation needed a contiguous memory block for user
ROM/RAM. This is because there was only 1 L3 page table which can only
map a contiguous memory area.

Also, remove the PMP configuration which just complicates things,
rely on the MMU mappings instead.
2022-06-20 21:24:18 +08:00
Jukka Laitinen
d8cc1fd76d arch/riscv/mpfs: Add a config flag to select SD mux state
This has been previously hard-coded to SD-card. Make it build time configurable.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-06-16 09:17:30 -03:00
Eero Nurkkala
5683e020e8 risc-v/mpfs: update clock configuration parameters
Update PLL configuration parameters to match the values provided
by the vendor.

Also remove extra call to mpfs_pll_config() as it's already called
at mpfs_clockconfig().

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-15 21:29:45 +08:00
Masayuki Ishikawa
a0ff6f9fa6 arch: k210: Add a workaround for clock stabilization
Summary:
- I noticed that sometimes uart shows nothing on the maix-bit board.
- This commit adds a workaround to avoid such the issue

Impact:
- k210 only

Testing:
- Tested with maix-bit

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-06-13 11:42:59 +08:00
Norman Rasmussen
e6376c72d7 Fix CONFIG_ALLSYMS for arm, risc-v and xtensa after #5496 2022-06-13 11:39:06 +08:00
Gustavo Henrique Nihei
59da1bc86a risc-v/esp32c3: Disable region protection on IDFboot for Flat build
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-11 01:55:46 +08:00
Gustavo Henrique Nihei
5805ad3954 risc-v/esp32c3: Disable access to invalid memory regions using MPU
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2022-06-11 01:55:46 +08:00
Ville Juven
16286081e1 risc-v/mpfs: Move the entry point to .start section
Remove the object linkage and use an explicit .start section
2022-06-10 20:18:23 +08:00
Eero Nurkkala
39d389545e risc-v/mpfs: usb: add composite support
This provides USB composite (CDC/ACM and Mass Storage) support
for mpfs board. In addition, a number of USB fixes are included:

 - Support for Setup Out packets
 - Proper support for larger than packet size writes
 - Finishing setup packets properly

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-06-09 20:44:40 +08:00
Jukka Laitinen
b7a1b75a3b arch/risc-v/src/mpfs/mpfs_start.c: Don't boot if DDR is enabled and training fails
Output "X" with showprogress and make a system reset.

Silently ignoring failed training is dangerous and will cause random behaviour if DDR is used

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-06-09 09:36:38 -03:00
Abdelatif Guettouche
326183bbbc esp32c3/Kconfig: Remove duplicate wireless config
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-06-09 20:19:35 +08:00
Xiang Xiao
f1236da21c fs: Make the binary(no process) mode as the default
POSIX require file system shouldn't enable the \r and \n conversion by default
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:22:26 +03:00
Xiang Xiao
28b25e0391 arch: dump "<noname>" as the task name if CONFIG_TASK_NAME_SIZE equals 0
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:17:23 +03:00
Xiang Xiao
2b2830c252 arch/assert: Replace twice strlcpy with single snprintf
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:17:23 +03:00
Xiang Xiao
b02db04e00 arch/assert: Keep the thread dump column order same as ps
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-07 20:17:23 +03:00