Commit Graph

125 Commits

Author SHA1 Message Date
chao an
d6747dd6ad libc/armv8-m: fix build break if MVE is disabled
machine/arm/armv8-m/gnu/arch_memcpy.S: Assembler messages:
machine/arm/armv8-m/gnu/arch_memcpy.S:105: Error: bad instruction `prologue push_ip=HAVE_PAC_LEAF'
machine/arm/armv8-m/gnu/arch_memcpy.S:121: Error: bad instruction `epilogue push_ip=HAVE_PAC_LEAF'
make[1]: *** [Makefile:143: bin/arch_memcpy.o] Error

Signed-off-by: chao an <anchao@xiaomi.com>
2023-05-05 08:07:08 +02:00
zhangyuan21
73257eeda0 libs/libc: fixed armv7-m strcmp build issue
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-04 11:59:41 -04:00
chao an
9fa097ab69 newlib: libc: memcpy M-profile PACBTI-enablement
Add function prologue/epilogue to conditionally add BTI landing pads
and/or PAC code generation & authentication instructions depending on
compilation flags.

Signed-off-by: chao an <anchao@xiaomi.com>
2023-04-28 09:51:52 +08:00
Stuart Ianna
4cae98674d litex: Support for kernel build with vexriscv-smp. 2023-04-22 01:40:32 +08:00
XinStellaris
57df1ddcbb Add armv7m assembly strcpy.
Signed-off-by: XinStellaris <tianxin7@xiaomi.com>
2023-04-10 18:59:52 +03:00
chao an
4fbf5f7a4b libs/libc: correct config define of arch functions
Signed-off-by: chao an <anchao@xiaomi.com>
2023-04-04 09:37:46 -03:00
Stuart Ianna
01b0305ab5 risc-v: SV32 MMU support for qemu-rv. 2023-03-29 22:15:19 +09:00
Xiang Xiao
2c5f653bfd Remove the tail spaces from all files except Documentation
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-26 13:24:24 -08:00
Xiang Xiao
8b4ecac6c2 libc: Move math library from libs/libc/math to libs/libm/libm
to prepare the support of other implementation e.g.:
https://github.com/JuliaMath/openlibm
https://gitlab.com/gtd-gmbh/libmcs

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-02-23 10:40:07 +02:00
Fotis Panagiotopoulos
85ceb7920e Typo fixes. 2023-02-17 11:17:11 -03:00
chao an
e942a7c55e build/Kconfig: fix warnings detected by kconfiglib
Signed-off-by: chao an <anchao@xiaomi.com>
2023-02-09 20:07:46 +08:00
Petro Karashchenko
f952b8456c assert: switch from ASSERT(0/false) to PANIC
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-01-26 10:15:34 +08:00
zhangyuan21
e34f79aa28 libc: don't redefined __ARM_ARCH_XXX when __ARM_ARCH defined
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-01-10 14:58:35 +02:00
zhangyuan21
fae5aef4fe libc: add arm64 libc function
Porting memory and string optimize functions from newlib and bionic

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-01-10 11:31:26 +08:00
zhangyuan21
f8f29c8147 libc: add risc-v libc function
Porting memory and string optimize functions from newlib and bionic

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-01-10 11:31:26 +08:00
zhangyuan21
fc9aeb8c70 libc: add armv7-r libc function
Porting memory and string optimize functions from newlib and bionic

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-01-10 11:31:26 +08:00
zhangyuan21
650f17169a libc: add armv7-a armv7-m armv8-m libc function
Porting memory and string optimize functions from newlib and bionic

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-01-10 11:31:26 +08:00
chao an
d12ddf56df arm/arm: sync ARM_THUMB support from cortex-a
Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-05 01:09:31 +08:00
chao an
4b70e4ff77 arm/cortex-r: sync ARM_THUMB support from cortex-a
Signed-off-by: chao an <anchao@xiaomi.com>
2022-12-04 20:12:31 +08:00
Tiago Medicci Serrano
d3ffeb40a7 libc/machine/xtensa: make longjmp safe against context switch
In order to turn longjmp context-switch safe, it's necessary
to disable interrupts before modifying windowbase and windowstart.
Otherwise, after a context switch, windowstart and windowbase
would be different, leading to a wrongly set windowstart bit due to
longjmp writing it based on the windowbase before the context switch.
This corrupts the registers at the next window overflow reaching
that wrongly set bit.

*Background:*
This PR is related to an issue first observed on ESP-IDF
https://github.com/espressif/esp-idf/issues/5229 and it was, then,
checked on NuttX using a test application.

*The test application:*
To check if the problem affects ESP32, ESP32-S2 and ESP32-S3 on
NuttX, it was created an application based on:
https://en.cppreference.com/w/c/program/longjmp

The application creates 16 tasks (`#define NUMBER_OF_TASKS  16`)
that implements the following daemon:

```
static int setjmp_longjmp_daemon(int argc, char *argv[])
{
  for (int i = 0; i < NUMBER_OF_TASKS * 2; i++)
    {
      jmp_buf env;

      volatile int count = 0;
      if (setjmp(env) != UINT16_MAX)
        {
          foo(&env, ++count);
        }
    }

  sem_post(&g_sem);

  return EXIT_SUCCESS;
}
```

The main function also initializes a semaphore to avoid application
exiting before tasks return successfully:

```
  sem_init(&g_sem, 0, -NUMBER_OF_TASKS);
```

Finally, the round-robin interval was lowered to 1ms to raise the
chances of the longjmp being interrupted by a context switch
(`CONFIG_RR_INTERVAL=1).

This setup was able to reproduce the problem prior to this patch
being applied.
2022-11-22 19:34:44 +01:00
Xiang Xiao
3e3364d1a9 Fix the format string mismatch warning
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-10-31 11:20:56 +01:00
Xiang Xiao
70290b6e38 arch: Change the linker generated symbols from uint32_t to uint8_t *
and remove the duplicated declaration

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-09-24 21:26:56 +02:00
chao an
a3a4e89efc libs/libc/arm: use builtin routines instead of aliases of __aeabi_mem*
Signed-off-by: chao an <anchao@xiaomi.com>
2022-09-24 00:10:36 +08:00
wangbowen6
4e1097280a telink: add custom setjmp implementation for tlsr82.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-09-08 09:15:25 +08:00
chao.an
62977ec4e8 arch/sim: add windows host simulate support
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-08-23 22:04:42 +08:00
chao.an
ca24efff80 libs/libc: correct config name
Signed-off-by: chao.an <anchao@xiaomi.com>
2022-07-27 20:18:05 +08:00
Nathan Hartman
849f760b77 Fix various typos 2022-07-08 02:15:54 +08:00
zhuyanlin
3455002ffd libc:xtensa:arch_memmove: fix warning
warning: 'SIM_CHECKS_ALIGNMENT' macro redefined
[-Wmacro-redefined] #define SIM_CHECKS_ALIGNMENT 1

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-06-07 11:09:57 +03:00
Xiang Xiao
1a3e57fe86 libc: Remove weak_function from __aeabi_atexit
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-06-02 10:54:23 +03:00
Ville Juven
622677d4a1 libc: Implement exit, atexit, on_exit and cxa_exit on the user side
For CONFIG_BUILD_KERNEL using the sched/task/task_exithook implementation
will just not work. It calls user code with kernel privileges which is
a bit of a security issue.
2022-05-25 15:28:43 +08:00
Xiang Xiao
51cf7ba05a Remove FAR from arm/risc-v/xtensa/sim/x86
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-15 13:55:58 +03:00
Xiang Xiao
f7f8a21486 libs: Move aeabi_atexit from libxx/ to libc/machine/arm/
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-05-13 00:13:03 +03:00
Masayuki Ishikawa
5c3d6bba6d libs: risc-v: Add R_RISCV_JAL support to arch_elf.c
Summary:
- This commit adds R_RISCV_JAL support to arch_elf.c
- The code only checks the immediate value but does not relocate it
  because it is done by the compiler.

Impact:
- None

Testing:
- Tested with rv-virt:knsh64 (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-05-12 10:36:03 +08:00
zhuyanlin
38f8032e31 libc:xtensa: move syscall to swint call
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-05-11 10:48:53 +02:00
wangbowen6
dcb440a4d9 libc/arch_atomic: add FAR to pointers.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-04-29 15:06:11 +08:00
wangbowen6
ea164f28b8 libc/arch_atomic: add gcc legacy __sync buitins support.
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-04-29 15:06:11 +08:00
wangbowen6
cbab540169 arm/arch_setjmp.S: armv6m support setjmp, longjmp
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
2022-04-27 23:21:03 +08:00
Ville Juven
9288ed85e7 RISC-V: Add/fix implementation for arch_elf.c
The jump instruction relocation had an assert that tests for jumps with
an offset of 0. This makes it so that a while(1); statement causes an
assert because the jump instruction points to the same address, which
is perfectly legal.

Addend was not handled correctly in several reloc types.

Add ADD32/64 + SUB32/64 relocations, for some reason the compiler
I use likes to add them.
2022-03-23 17:56:54 +08:00
zhuyanlin
5665b7a585 arch:lib_atomic: remove and fix gcc warning declaration-mismatch
Remove GCC ignored warning and fix

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-03-18 13:35:42 +08:00
Huang Qi
69cfe8d626 arch/arm: Support setjmp/longjmp for all socs
After check the official specification of ARM ISA
and Thumb ISA, the arch_setjmp_thumb.S are written
by arm unified assembly language,
so it easy to make it works for ARM and thumb ISA.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-09 17:13:21 +02:00
Huang Qi
c6e636a871 arch/risc-v: Save/Load float register in setjmp
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-09 10:15:54 +02:00
Huang Qi
cfff115f21 arm: Move setjmp to common place
Since some Cortex A core supports thumb mode also,
thus they can share same implementation.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-03-08 21:00:29 +08:00
Masayuki Ishikawa
de95a8550f arch, board: Add thumb support to i.MX6
Summary:
- This commit adds thumb support to i.MX6
- Also, applies the same coding style to arch_elf.c

Impact:
- i.MX6 only

Testing:
- Tested with sabre-6quad:smp (QEMU, Dev board)
- Tested with sabre-6quad:netnsh (QEMU)
- Tested with sabre-6quad:netknsh (QEMU, not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-25 10:51:12 +08:00
Masayuki Ishikawa
11731125ef libs: armv7-a: Add thumb support to arch_elf.c
Summary:
- This commit adds thumb support to arch_elf.c

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (QEMU, not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-02-25 10:51:12 +08:00
zhuyanlin
1aedf30f38 libc:machine:xtensa: fix warning
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-02-24 22:13:46 +08:00
Xiang Xiao
928d52f315 libc/machine: Implement ARM aeabi_xxx API called by clang
specified here:
https://developer.arm.com/documentation/ihi0043/latest

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-21 09:29:18 +01:00
Xiang Xiao
1d1bdd85a3 Remove the double blank line from source files
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-20 20:10:14 +01:00
Peter Kalbus
6abdf73535 sim: Initial support on MacOS M1 and Linux AARCH64 based hosts. 2022-02-17 09:35:09 +08:00
Oki Minabe
c1ea37742b fix arm FPSCR typos in comments. 2022-02-17 01:08:11 +08:00
Xiang Xiao
5f67662c63 libc/sim: Rename arch_setjmp[64].S to arch_setjmp_x86[_64].S
to follow other arch/x86 arch/x86_64 convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-02-16 12:23:16 +08:00