'rcS' will case files that has duplicate name been replaced.
so on the Mac platform we use 'q' instead of 'r' to achieve an
effect similar to '-P'
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
The board-level GPIO support is different from the already existing
button and LEDC support because it enable us to register the GPIO
pins as devices in `/dev/gpioX`. Some applications are able to use
this interface to read and write the GPIO pins.
Documentation was added regarding its usage. Please check
`Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst`
to fix the following linker error:
/usr/bin/ld: nuttx.rel: in function `aes_encrypt_xform':
/github/workspace/sources/nuttx/crypto/xform.c:509: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_decrypt_xform':
/github/workspace/sources/nuttx/crypto/xform.c:514: undefined reference to `aes_decrypt'
/usr/bin/ld: nuttx.rel: in function `aes_setkey_xform':
/github/workspace/sources/nuttx/crypto/xform.c:519: undefined reference to `aes_setkey'
/usr/bin/ld: nuttx.rel: in function `aes_ctr_crypt':
/github/workspace/sources/nuttx/crypto/xform.c:566: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_ctr_setkey':
/github/workspace/sources/nuttx/crypto/xform.c:585: undefined reference to `aes_setkey'
/usr/bin/ld: nuttx.rel: in function `aes_ofb_encrypt':
/github/workspace/sources/nuttx/crypto/xform.c:694: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_ofb_setkey':
/github/workspace/sources/nuttx/crypto/xform.c:706: undefined reference to `aes_setkey'
/usr/bin/ld: nuttx.rel: in function `aes_cfb8_encrypt':
/github/workspace/sources/nuttx/crypto/xform.c:733: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_cfb8_decrypt':
/github/workspace/sources/nuttx/crypto/xform.c:751: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_cfb128_encrypt':
/github/workspace/sources/nuttx/crypto/xform.c:765: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_cfb128_decrypt':
/github/workspace/sources/nuttx/crypto/xform.c:781: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_gmac_setkey':
/github/workspace/sources/nuttx/crypto/gmac.c:135: undefined reference to `aes_setkey'
/usr/bin/ld: /github/workspace/sources/nuttx/crypto/gmac.c:143: undefined reference to `aes_encrypt'
/usr/bin/ld: nuttx.rel: in function `aes_gmac_final':
/github/workspace/sources/nuttx/crypto/gmac.c:195: undefined reference to `aes_encrypt'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
1. the defconfig is based on nuttx/boards/sim/sim/configs/nsh/defconfig
2. make the option enabled by default that needed by open posix
testsuite, such as PTHREAD_SPINLOCK, FS_AIO, TESTING_LTP etc.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
Some SD card connectors do not have separate card detection pin. In that
case card detection has to be done on CD/DAT3 data line. This means
software (i.e. architecture level driver) has to take care of pin
configuration switching (pin has to be set as data pin in case of
transfer and as interrupt card detection pin when there is no action
on data line).
This commit adds CD/DAT3 line card detection support for SAMv7 MCU.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
The class device only handles descriptor information specific to the class,
and shared descriptor information is passed through parameters and
handled by the composite driver.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Provide initial support for audio through the I2S peripheral to the
CS4344 audio codec on ESP32-S3-DevKitC-1 board.
Please check documentation for usage examples.
A usbdev has only one serial string, so use a unique macro to control it.
For boards that enable board serial string using COMPOSITE_BOARD_SERIALSTR,
PL2303_BOARD_SERIALSTR, CDCACM_BOARD_SERIALSTR, USBADB_BOARD_SERIALSTR,
USBMSC_BOARD_SERIALSTR, and RNDIS_BOARD_SERIALSTR, they need to be replaced
with BOARD_USBDEV_SERIALSTR.
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
SiFive document: "ECC Error Handling Guide" states:
"Any SRAM block or cache memory containing ECC functionality needs to be
initialized prior to use. ECC will correct defective bits based on memory
contents, so if memory is not first initialized to a known state, then ECC
will not operate as expected. It is recommended to use a DMA, if available,
to write the entire SRAM or cache to zeros prior to enabling ECC reporting.
If no DMA is present, use store instructions issued from the processor."
Clean the cache at this early stage so no ECC errors will be flooding later.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
When I try to set priorities in certain programs, such as init_priority(HIGH_PRIORITY), I've noticed that during linking, there's no guarantee that the programs will be compiled in the sequence I've specified based on priority. This has led to some runtime errors in my program.
I realized that in the ld file, when initializing dynamic arrays, there's no assurance of initializing init_array.* before init_array. This has resulted in runtime errors in the program. Consequently, I've rearranged the init_array.* in the ld file of NuttX to be placed before init_array and added a SORT operation to init_array.* to ensure accurate initialization based on priorities during linking.
update LIBFDT to LIBC_FDT
update CONFIG_LIBFDT_DTC_VERSION to CONFIG_LIBC_FDT_DTC_VERSION
move dtc source code to fdt/dtc
move version_gen.h from apps/system/fdt to current dir
Signed-off-by: liaoao <liaoao@xiaomi.com>
This patch starts to implement the ability to build Meadow.OS for the Meadow F7 board with the NuttX mainline. It will be followed by more patches, progressively enabling full Meadow.OS functionality. This configuration is a work in progress.
The Meadow.OS source code is needed to build this configuration. Meadow.OS is being open-sourced under the Apache 2.0 license. A prototype of the source code release and integration with NuttX is at https://github.com/WildernessLabs/Meadow.OS/tree/prototype
This is the second revision of this patch, as the first one (https://github.com/apache/nuttx/pull/9997) was causing build issues on NuttX CI and was reverted.
This should only impact the Meadow F7 board configurations.
No testing to be done, as the configuration is under development.
Move SCU-specific ak09912 sensor into spresense board layer.
Rename a function name to register SCU sensor driver
from ak09912_register to ak09912_scu_register.
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
make debug print hex again add board include
Pinephone Pro port just nsh
Status:
booting till GICD / IRQ issue
style cleanups
start to fix style checks
revert offset
whitespaces
revert a64 bringup file
prob last cleanup
more cleanups
remove dts
move changes from a64 hardware specific folders to rk3399
undo common changes (except head.s)
revert gitignore
missing irq.h and rk3399_serial.c need to finish cleaning them up
WIP
add source for load address
remove ccache, add board memory map
remove board reset
Summary:
- I noticed that device discovery for virtio-mmio devices does not
work without bus=virtio-mmio-bus.x option. Without this option,
qemu assigns the virtio device into the virtio-mmio space
in reverse order automatically.
- To fix this issue, we must specify the correct numbers for the
target machines. (i.e. arm32/64->32, rv32/64->8)
Impact:
- None
Testing:
- Tested with qemu-7.2.4
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Decreasing the value may increase DQ/DQS window size. Keep the default value
(1) for the existing board configurations.
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
Adds a platform specific implementation for tickless schedular operation. This includes:
- Tickless operation for vexriscv cores.
- Tickless operation for vexriscv-smp cores.
- Ticked operation for vexriscv-smp cores.
Ticked operation for vexriscv core has been refactored.
Additional default configuration added to demonstrate operation.
Both tickless and ticked options use Litex timer0 for scheduling intervals. This is significantly faster than interfaceing with the risc-v mtimer through opensbi.
ESP32-S3 has only one 2.4 GHz ISM band RF module, which is shared
by Bluetooth and Wi-Fi, so Bluetooth can’t receive or transmit data
while Wi-Fi is receiving or transmitting data and vice versa.
Under such circumstances, ESP32-S3 uses the time-division
multiplexing method to receive and transmit packets.
Supported external SDRAM (MT48LC4M32B2B5-6AIT:L) on STM32H745I-DISCO dev board.
Though MT48LC4M32B2B5-6AIT:L SDRAM itself provides 32-bit data bus, STM32H745I-DISCO board
routes only DQ[15:0] bits. Thus only half of the memory can be accessed: the accessible memory
configuration is only 1 Meg x 16 x 4 banks instead of 1 Meg x 32 x 4 banks.
Thus the accessible memory size is 8 MBytes.
Testing:
nsh> ramtest -a 0xD0000000 -s 8388608
RAMTest: Marching ones: d0000000 8388608
RAMTest: Marching zeroes: d0000000 8388608
RAMTest: Pattern test: d0000000 8388608 55555555 aaaaaaaa
RAMTest: Pattern test: d0000000 8388608 66666666 99999999
RAMTest: Pattern test: d0000000 8388608 33333333 cccccccc
RAMTest: Address-in-address test: d0000000 8388608
nsh>
Adding the CONFIG_ARCH_PERF_EVENTS configuration to enable
hardware performance counting，solve the problem that some platform
hardware counting support is not perfect, you can choose to use
software interface.
This is configured using CONFIG_ARCH_PERF_EVENTS, so weak_functions
are removed to prevent confusion
To use hardware performance counting, must:
1. Configure CONFIG_ARCH_PERF_EVENTS, default selection
2. Call up_perf_init for initialization
Signed-off-by: wangming9 <wangming9@xiaomi.com>
The default mode for Rpmsgdev is to read/write data as long as possible for
caller, this mode does not apply to tun devices, tun devices can read and
write only one complete ip packet at a time.
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
Summary
Qemu virt board can choice CPU core with boot parameter
and we need to add Konfig option for choice
the change do this
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
Sumary
add hostfs support for arm64, it's a copy
from arm32.
Note:
it's not support for opendir and readdir, command
like ls will not work.
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
