Author: Alan Carvalho de Assis <acassis@gmail.com>
Fix long line comments in the header files
Author: Mateusz Szafoni <raiden00pl@users.noreply.github.com>
* arch/arm/src/nrf52: add GPIOTE and SAADC registers definitions
* arch/arm/src/nrf52: update some registers definitions
* arch/arm/src/nrf52: add basic I2C support
* arch/arm/src/nrf52: add function to unconfigure GPIO
* arch/arm/src/nrf52/nrf52_lowputc: add missing FAR
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run all .h and .c files modified in last PR through nxstyle.
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Fix stm32l4_otgfshost.c: error: 'ret' undeclared (#32)
result by commit 6a3c2aded6
Change-Id: I68ba79417d8da102da8d91c74496961aef242dd9
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Run all .c and .h files in last PR through tools/nxstyle and fix all complaints.
Author: macman88 <jjlange91@gmail.com>
LPC17xx serial updates (#29)
* Save CONFIG_ARCH_BOARD_CUSTOM when running 'make savedefconfig'
* Don't compile up_earlyserialinit if USE_EARLYSERIALINIT is not defined
* Added support for RS485 direction control on LPC17xx UART1
* First pass at fractional baud rate divider on LPC17xx/40xx
* Added support for fractional divider to console UART
Author: patacongo <spudarnia@yahoo.com>
arch/arm/src/imxrt/imxrt_enet.c: Fix some warnings found in build testing.
Also fix coding standard problems reported by nxstyle. (#26)
Co-authored-by: Gregory Nutt <gnutt@nuttx.org>
Run all .c and .h files in last PR through nxstyle.
Author: macman88 <jjlange91@gmail.com>
SAME5x Ethernet Support (#25)
boards/arm/samd5e5/same54-xplained-pro/: Adds basic support for Microchip SAM E54 Xplained Pro board.
arch/arm/src/samd5e5/: Adds an Ethernet driver for the SAME5x family (based on the SAMA5 GMAC driver).
* Simplify EINTR/ECANCEL error handling
1. Add semaphore uninterruptible wait function
2 .Replace semaphore wait loop with a single uninterruptible wait
3. Replace all sem_xxx to nxsem_xxx
* Unify the void cast usage
1. Remove void cast for function because many place ignore the returned value witout cast
2. Replace void cast for variable with UNUSED macro
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run all .h and .c files modified in last PR through nxstyle.
Author: Minamiya_Natsuki <yukihiratype2@gmail.com>
Add FMC SDRAM for STM32H7x3 chip (#22)
* Add FMC SDRAM for STM32H7x3 chip
* Add FMC SDRAM for STM32H7x7
* Nuttx Coding Standard requires one declaration per line
* should be __ARCH_ARM_SRC_STM32H7_STM32_FMC_H
* fix bad alignment
* fix typo
* fix typo
* people can't live in furture
* fix comment line length
* fix more comment line length
* fix aligenment
* fix typo
Author: Gregory Nutt <gnutt@nuttx.org>
Run all .c and .h modified in PR through nxstyle.
Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
feature k210 (#16)
* arch: risc-v: Add support for __LP64__ to types.h
* arch: risc-v: Add support for RV64GC to common files
* arch: risc-v: Add support for Kendryte K210 processor (RV64GC)
* boards: risk-v: Add support for Sipeed Maix Bit with K210
* tools: Add support for Kendryte K210 processor
arch/arm/src/sama5/sam_serial.c: uart2port in sam_serial, fix the rest of the uarts in sam_serial
boards/arm/sama5/sama5d2-xult/README.txt: Fix some minor typos
boards/arm/sama5/sama5d2-xult/include/board.h: Update UART pin disambiguation with default UARTn_RXD, _TXD
STM32L4_NUSART was set to 4. The spec at
https://www.st.com/resource/en/datasheet/stm32l433cc.pdf states the
following on page 1:
- 4x USARTs (ISO 7816, LIN, IrDA, modem)
- 1x LPUART (Stop 2 wake-up)
However it on page 49, it states:
The STM32L433xx devices have three embedded universal synchronous
receiver transmitters (USART1, USART2 and USART3).
The latter is correct.
This patch sets STM32L4_NUSART to 3.
Code was flawed in that the Pins are defined with the
pullups in the definition. Since there are no alterntes pins
there is no way to remove them. So not enabling the CONFIG
pull up did nothing as did enabling them.
Code also ignored the use of D0 for ready detection causing
3X+ the chatter.
This is now a compile time feature as there was no reason for
it to be a run time. It wasted both flash and ram.
Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
Ran nxstyle against many of the affected files. But this job was too big for today. Many of the network drivers under arch are highly non-compiant and generate many, many faults from nxstyle. Those will have to be visited again another day.
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
This effects all network drivers as well as timing related portions of net/: devif_poll_tcp_timer shouldn't be skipped in the multiple card case. devif_timer will be called multiple time in one period if the multiple card exist, the elapsed time calculated for the first callback is right, but the flowing callback in the same period is wrong(very short) because the global variable g_polltimer is used in the calculation. So let's pass the delay time to devif_timer and remove g_polltimer.
Fix fe310 signal handling
* arch: fe310: Disable all interrupts in mie at __start
* arch: fe310: Fix up_irq_enable() to set external interrupt only
* arch: fe310: Fix up_schedule_sigaction() to save REG_INT_CTX
* boards: hifive1-revb: Adjust stack size to reduce runtime memory
Approved-by: Gregory Nutt <gnutt@nuttx.org>
nrf52 updates
board/arm/nrf52/nrf52832-dk: use the on-board virtual COM pins as default UART0 configuration
board/arm/nrf52: initial support for the nrf52840-dk board
board/arm/nrf52: initial support for the nrf52840-dk dongle board
arch/arm/src/nrf52: add support for port 1 GPIO
arch/arm/src/nrf52: initial support for UART1
arch/arm/src/nrf52: add UICR definitions
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Sparkfun RED-V Things Plus
* board: hifive1-revb: Update README-qemu.txt
* arch: fe310: Works with SparkFun RED-V Things Plus
Should work with HiFive1 Rev.B but not tested yet.
* boards: hifive1-revb: Works with SparkFun RED-V Things Plus
Should work with HiFive1 Rev.B but not tested yet.
Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
riscv updates
* arch: risc-v: Remove up_dumpstate.c because the file had been merged into up_assert.c
* boards: gapuino: Modify Makefile which conforms to NuttX standards
* boards: nr5m100-nexys4: Modify Makefile which conforms to NuttX standards
Approved-by: Gregory Nutt <gnutt@nuttx.org>
HiFive1 with qemu
* arch: risc-v: Add include/.gitignore
* arch: risc-v: Add src/.gitignore
* arch: risc-v: Remove uncommon function prototypes in include/irq.h
* arch: risc-v: Add missing symbols and function prototypes in src/common/up_internal.h
* arch: risc-v: Add src/common/up_modifyreg32.c
* arch: risc-v: Enable include Make.dep in src/Makefile
* arch: risc-v: Fix stack coloration in common/up_createstack.c
* arch: risc-v: Add common/up_puts.c
* arch: risc-v: Add common/up_checkstack.c
* arch: rv32im: Move all logics from up_dumpstate.c to up_assert.c
This change is same as other architectures like arm/src/armv7-m
* arch: Select ARCH_HAVE_STACKCHECK for RISC-V in Kconfig
* arch: risc-v: Add SiFive fe310 processor
NOTE: Currently only tested with qemu
* boards: hifive1-revb: Add SiFive hifive1-revb board
NOTE: Currently only tested with qemu
* tools: Add fe310 processor to configure.sh
Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM23L4 LPTIM PWM support with multi-channel
* arch/arm/src/stm32l4/stm32l4_pwm.c:
fixed some bugs
arch/arm/src/stm32l4/stm32l4_pwm.h:
support LPTIM PWM if PWM multi-channel is selected
Channel mode for LPTIM are not available
* arch/arm/src/stm32l4/Kconfig: add new configuration for STM32L4 LPTIM support
* arch/arm/src/stm32l4/stm32l4_pwm.c: fix warning: resetbit may be used uninitialized
Approved-by: Gregory Nutt <gnutt@nuttx.org>
I did suspect that it was just about possible that there's a use for this check (specifically, when you're changing serial the clock immediately after the character is sent) but since we're only testing that the character has left the holding register and not that it's actually been sent to line I don't think it's valid even for this case.
Driver update
* drivers/mtd/Make.defs: Add MTD driver for QuadSPI-based Winbond NOR FLASH
* stm32l4/stm32l4_qspi.c: the "QSPI_DMA_PRIO" has been defined above
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards/arm/stm32h7/stm32h747i-disco: Remove references to nucleo in the stm32h747i-disco board.
arch/arm/include/stm32h7, arch/arm/src/stm32h7, and boards/arm/stm32h7/stm32h747i-disco: Add support for the STM32H747I-DISCO board.
1) Operational issue
TC (Transmission complete) and TDRE (TX Buffer Empty) were transposed in imxrt_serial.c. The end result was that for unoptimised code everything worked fine, but optimised code got itself into a real mess and continually fired interrupts. The patch attached fixes this. This one would have been found much more quickly if this particular board had supported SWO :-/
2) Startup issue
There are a number of chip errata that apply to the 1052 first revision (A-suffix) that don't apply to the second (B-suffix). Those got me for a while and it's important to use an EVK_B_ dev board if you're suffering stability problems with this particular chip. However, even with that resolved with either optimised or unoptimised code when there is no SNVS (Battery Backup) power and the power is switched on the CPU appears to boot but gets stuck with timer interrupts not being generated. The CPU is running and it will execute linear code. I have determined this by putting an 'imxrt_lowputc('A'+irq)' into up_doirq. For the non-running case the output looks like this;
LLLL
this implies 4 0x0b interrupts have been generated, and nothing else. If I hit keys on the keyboard I get 'e' in the flow. 0x0b is the SVC instruction and is the mechanism by which NuttX handles task switching. 'e' is 0x24, which corresponds to the LPUART1 interrupt. Other than these, the system does not respond further but is happily in the idle loop. In this circumstance if you hit SW2 on the EVKB board though the logjam 'unjams' and normal service is established, output now looks like;
LLLLPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPLPP ...etc.
Where 'P' is 0x0f (the SYSTICK interrupt)....this is what _should_ be happening so; SYSTICK starts up after SW2 has been pressed.
From this point on everything works correctly and you can reboot the CPU, put new code into it or do whatever you wish, **provided power is not cycled off**. If power is cycled off then return to the top and go through the process again.
When there is SNVS power to the CPU then power can be switched on and off as you wish, and the CPU will boot correctly. This has been determined by putting 3V onto J6.
I think we are probably doing something naughty with the way we are starting the clocks to the timers. There are certainly some restrictions on imxrt clock manipulation which we have studiously avoided. I am investigating further and have some potential patches but even if I find the root cause it should not be included in 8.2 as the change could be disruptive.
https://github.com/zephyrproject-rtos/zephyr/pull/8535/commits: "The imxrt1050 is configured to use SYSTICK for the kernel timer, but SYSTICK cannot wake up the soc from low-power modes. Disable low-power modes on this soc until we have support for an alternative timer."
"This fixes k_sleep on the EVKB version of the mimxrt1050_evk board. An earlier version of the board (EVK, not EVKB), had A0 silicon which by default did not enter low-power mode on a wfi."
This patch reverts the WFI enable for further investigation post 8.2. With this patch in place together with the previous one my system is fully stable(*), just drinking a bit more power than I'd like.
This change decouples that upper activity-based logic from the lower random walk logic and allows use of other upper state detection logic (such as a custom, application-specific state machine).
(1) unifies the iomux definitions - previously some pins had them, and some didn't. This effectively made it impossible to use the pinmuxes without editing the header file in the standard distribution tree.
(2) unifies the pin definitions so that every pin now has a suffix. This makes it *much* easier to see when a pin is in use in your code, because it will always have a definition in your board.h file.
For anyone who is already using this CPU, a couple of small changes are needed to existing code;
In respect of (1) add IOMUX decorators to your pin definitions. You will find defaults in haardware/imxrt_iomux.h. Every pin should have a IOMUX decorator and in general the defaults should be OK. So while previously in your board.h file you might have had;
You will now have;
In respect of (2) you will need to add selectors for any function that previously only had one pinning option. There aren't many of those but LPUART1 is a good example. That just means adding into your board.h something like;
STM32H7:Set the BBSRAM memory range to non-cacheable.
* armv7-m:mpu add user peripheral helper
* stm32h7:BBSRAM Exclude BBSRAM from cacheable when CONFIG_ARMV7M_DCACHE
ST placed the STM32H7 BBSRAM in the SRAM default memory region
which is cacheable. This commit sets the BBSRAM memory range
to non-cacheable.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/tiva/common/tiva_flash.c: Fix several mistakes in
tiva_write() but note that this function needs more work. (1) Fix wrong
use of && when & was intended. (2) Add compile- time warning directive
because according to this function's interface, it is supposed to
support unaligned writes and/or writes of arbitrary numbers of bytes to
FLASH. However, this function does NOT support that at this time. This
needs to be fixed. (3) Fix wrong preprocessor conditional. Was written
to use the 32-word write buffer only for TM4C1294NCPDT. This buffer is
available on all TM4C123 and TM4C129 parts. Now conditioned upon
CONFIG_ARCH_CHIP_TM4C123 or CONFIG_ARCH_CHIP_TM4C129. (4) Add comments
to document the intent of the above preprocessor logic.
stm32l4_otgfs: enable OTGFS for STM32L4+ series
The OTGFS peripheral on stm32l4x6 and stm32l4rxxx reference manual is
exactly the same. This patch also adds missing bits and fixes errors in
stm32l4x5xx and stm32l4x6xx OTGFS register maps.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Add DMA support for STM32L4+ series
* Add DMA support for STM32L4+
* stm32l4xrxx_rcc: enable "Range 1 boost" mode if any PLL freq above 80 Mhz
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards: cxd56xx: spresense: cleanup and new defconfig
* arch: cxd56xx: remove NVIC_SYSH redefinition
The NVIC_SYSH is already defined in nvicpri.h
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: configs: enable SPRESENSE_EXTENSION
Enable high current mode for the Spresense Extension board on all examples
that have SDCARD support
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: ifdef SDCARD_TXS02612
The SD Card TXS02612 port expander is hosted on the Extension board and
should not be enabled if the extension board is not prezent.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: configs: increase MQ_MAXMSGSIZE
This change is needed by the display driver on spresense platform
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: config: add lcd examples defconfig
This is a configuration for the basic nx examples
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards: cxd56xx: spresense: add board_timerhook function
* boards: cxd56xx: spresense: add board_timerhook function
in preparation for SDK we muts have a weak board_timerhook function
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* drivers: usbhost: add missing endif
By accident an endif was missing.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: audio: add build barrier
The audio implementation should not be beuilt if the config
CONFIG_CXD56_AUDIO is not set.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch:arm:cxd56xx: add ge2d.h header
The header is used by imageproc.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
