Commit Graph

20625 Commits

Author SHA1 Message Date
zhangyuan21
841b178782 assert: show stacks with the sp from regs
1. Get the value of sp from dump regs when an exception occurs,
   to avoid getting the value of fp from up_getsp and causing
   incomplete stack printing.
2. Determine which stack the value belongs to based on the value
   of SP to avoid false reports of stack overflow

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-05 13:40:04 +08:00
Stuart Ianna
dec80be431 arch/risc-v/litex: Fix emac driver compilation when only IPv6 is used. 2023-05-05 11:53:13 +08:00
Lucas Saavedra Vaz
58f59fe9dc arch/xtensa/esp32s2: Fix SPIRAM compilation warnings
This commit aims to fix compilation warnings that happens when enabling SPIRAM for ESP32-S2
2023-05-04 18:41:54 -03:00
Lucas Saavedra Vaz
a5a3b919a0 audio: Add i2s_getmclkfrequency function
Rename i2s_mclkfrequency to i2s_setmclkfrequency and add i2s_getmclkfrequency for getting the current MCLK frequency from the I2S interface
2023-05-04 18:41:54 -03:00
simbit18
fcba68513d arch: Fix nxstyle errors
error: Long line found
2023-05-04 23:21:51 +03:00
fangxinyong
06f8875c0c arch/sim: do not free memory of zero-length reallocation
Follow the change: https://github.com/apache/nuttx/pull/9151,
if MM_CUSTOMIZE_MANAGER is enabled, heap memory manager in host is used,
for example in sim:asan build.

malloc and related allocation APIs will fall back to host_realloc,
do not free memory of zero-length reallocation. So memory allocations
return valid pointer when request zero size in all sim build.

call stack:
    malloc()         (mm/umm_heap/umm_malloc.c)
    mm_malloc()      (arch/sim/src/sim/sim_heap.c)
    mm_realloc()     (arch/sim/src/sim/sim_heap.c)
    host_realloc()   (arch/sim/src/sim/posix/sim_hostmemory.c)
    host_memalign()  (arch/sim/src/sim/posix/sim_hostmemory.c)

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2023-05-05 00:19:28 +08:00
chao an
1be95c3313 sim/lsan: disable fast-unwind by default
The fast-unwind implementation of leak-sanitizer will obtain the
current stack top/bottom and frame address(Stack Pointer) for
backtrace calculation:

https://github.com/gcc-mirror/gcc/blob/releases/gcc-13/libsanitizer/lsan/lsan.cpp#L39-L42

Since the scheduling mechanism of NuttX sim is coroutine
(setjmp/longjmp), if the Stack Pointer is switched, the fast-unwind
will unable to get the available address, so the memory leaks on the
system/application side that cannot be caught normally. This PR will
disable fast-unwind by default to avoid unwind failure.

Signed-off-by: chao an <anchao@xiaomi.com>
2023-05-04 18:05:22 +03:00
Tiago Medicci Serrano
28361a295d esp32/wifi: add support to WPA3 on Station Mode
Add support to select WPA3-SAE while connecting to an AP. Please
note that STA mode sets a security threshold, i.e, it was able to
connect to a WPA3-SAE network prior to this change because it
connects to an equally or more secure network than the set
threshold. Considering this patch, the device is now able to
ignore WPA2-PSK APs when WPA3 is set.
2023-05-03 23:23:31 +08:00
Tiago Medicci Serrano
9ede7d4650 esp32s3/wifi: add support to WPA3 on Station Mode
Add support to select WPA3-SAE while connecting to an AP. Please
note that STA mode sets a security threshold, i.e, it was able to
connect to a WPA3-SAE network prior to this change because it
connects to an equally or more secure network than the set
threshold. Considering this patch, the device is now able to
ignore WPA2-PSK APs when WPA3 is set.
2023-05-03 23:23:31 +08:00
zhangyuan21
884be2bdb9 assert: Distinguish between assert and exception
CURRENT_REGS may change during assert handling, so pass
in the 'regs' parameter at the entry point of _assert.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-05-03 14:49:32 +08:00
Lwazi Dube
e2083354f1 arch/arm/sama5: Use a recursive mutex to fix OHCI deadlock.
Unplugging a USB device from an OHCI root hub will cause
a deadlock if DRVR_EPFREE is called from sam_rhsc_bottomhalf. A
typical call chain looks like this: sam_rhsc_bottomhalf->
CLASS_DISCONNECTED->usbhost_destroy->DRVR_EPFREE. In this case
DRVR_EPFREE tries to lock a locked mutex. A recursive mutex
prevents this deadlock.
2023-05-03 12:53:30 +08:00
simbit18
79574c18d8 arch: Fix nxstyle errors
error: Long line found
2023-05-02 18:31:40 -06:00
Xiang Xiao
3c54e66683 mtd/nand: Fix the comment and remove the uneeded inclusion
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-05-01 22:47:00 +03:00
TimJTi
9c66f14e38 SAMA5D2 Class D 2023-04-29 13:46:04 +08:00
simbit18
eed360c0ad arch: Fix nxstyle errors
error: Long line found
2023-04-28 15:00:33 -03:00
zhangyuan21
f48693eaf5 arch: Return directly when arch not support interrupt context save
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-27 23:21:05 +03:00
simbit18
20faf08930 arch/avr/include/avr/avr.h: Fix nxstyle errors
error: Long line found
2023-04-27 23:20:40 +03:00
Ville Juven
7184d1f5f9 arch/risc-v: Fix save/load FPU macros
The macros destroy t0, t1, t2 when used, make them explicitly restore them
so they are safe to use from where-ever
2023-04-28 00:54:39 +08:00
zhangyuan21
4a4386c822 Revert "arch/armv7ar: use robust code sequences for cache maintenance"
This reverts commit 69fd539886.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-27 20:21:57 +08:00
zhangyuan21
89ae45be18 arch/risc-v: change up_saveusercontext to assembly code
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-27 17:34:30 +08:00
Radek Pesina
a0e2f29bdf Add option for selecting coherent DMA. 2023-04-27 16:41:00 +08:00
chao an
60d188353c arm/unwind: EABI unwind needs frame pointer support
Signed-off-by: chao an <anchao@xiaomi.com>
2023-04-27 16:38:40 +08:00
zouboan
4b5c18b9b2 arm/Toolchain.defs: fix error sed:-e expression #1,character 1:unknown command:' in Windows native build
arm/Toolchain.defs: fix error sed:-e expression #1,character 1:unknown command:' in Windows native build
2023-04-27 00:32:15 +08:00
chao an
8687fe1b9f sim/usbdev: fix unpaired critical_section() 2023-04-27 00:31:31 +08:00
Radek Pesina
50a8ec62c4 Add eMMC driver support
- Fix DMA addressing issues within litex_sendsetup/litex_recvsetup
- Extend with handling specific to eMMC commands during init & use.
- Cleanup of 4-bit BUS handling for SD and eMMC
- For eMMC, Send CMD0 during init as per JEDEC v4.41 for pre-idle
2023-04-26 00:34:36 -04:00
zhangyuan21
eb0e05be0d arch/armv7-r: add armv7-r smp support
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-26 10:54:30 +08:00
jturnsek
bcc8801480 Initial FlexIO support 2023-04-26 10:16:18 +08:00
Michal Lenc
40d07760f6 samv7: add support for adjtime() interface
This commit adds deifiniton of get_timer_period() and adj_timer_period()
functions used by adjtime() interface.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2023-04-25 14:37:50 -03:00
Fotis Panagiotopoulos
70e42f5bfe stm32_f7/h7_eth: Added error handling for abnormal interrupts. 2023-04-25 15:20:09 +02:00
Robert-Ionut Alexa
f2530c53a5 esp32: port support for I2C_M_NOSTART and I2C_M_NOSTOP
Signed-off-by: Robert-Ionut Alexa <robertalexa2000@gmail.com>
2023-04-25 20:35:55 +08:00
Ville Juven
d48114a4b7 sched/addrenv.c: Implement re-entrancy for addrenv_select()
Store the old environment in a local context so another temporary address
environment can be selected. This can happen especially when a process
is being loaded (the new process's mappings are temporarily instantiated)
and and interrupt occurs.
2023-04-25 14:33:19 +02:00
Ville Juven
20623d7369 sem/sem_init: Change sem_xxx -> nxsem_xxx in kernel modules
Use the kernel space api nxsem_xxx when inside the kernel.
2023-04-25 13:41:51 +02:00
zhangyuan21
6605f95133 l2cc: Do not repeat disabling the cache when the cache is already disabled
When l2cc is already in disable state, performing a disable operation
again will flush incorrect cache data to memory

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-25 15:36:10 +08:00
zhangyuan21
69fd539886 arch/armv7ar: use robust code sequences for cache maintenance
Invalidate operations at DDI0246H_l2c310_r3p3_trm:
If there is a stale entry in the L2 cache, the system enables the invalidation of
the L1 cache. But before the controller invalidates the L2 cache, it allocates a
line from the L2 cache to an L1 cache.

The robust code sequence for invalidation with a non-exclusive cache arrangement is:
1. InvalLevel2 Address ; forces the address out past level 2
2. CACHE SYNC ; Ensures completion of the L2 inval
3. InvalLevel1 Address ; This is broadcast within the cluster
4. DSB ; Ensure completion of the inval as far as Level 2.

This sequence ensures that, if there is an allocation to L1 after the L1 invalidation, the data
picked up is the new data and not stale data from the L2

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-25 15:35:37 +08:00
Masayuki Ishikawa
fb6bef2c2d arch: imx6: Add support for AR8031 gigabit ethernet phy
Summary:
- This commit adds AR8031 gigabit ethernet phy for the
  sabre-6quad board.

Impact:
- None

Testing:
- Tested with sabre-6quad:netnsh_ar8031 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-04-25 11:45:19 +08:00
Masayuki Ishikawa
dc914f43ea arch: imx6: Fix CONFIG_IMX_ENET_ENHANCEDBD related code
Summary:
- This commit applies the changes from imxrt
- See 3a4542f3c4

Impact:
- imx6 ethernet with d-cache

Testing:
- Tested with imx6_with_ar8031 (will be added later)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-04-25 11:45:19 +08:00
Petro Karashchenko
3e3670af77 arch/xtensa/esp32: fix wrong enabled BLE interrupts
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-04-24 09:35:58 -07:00
Petro Karashchenko
0c28094059 arch/xtensa/esp32: fix crash in BLE startup
ROM symbols provided by linker are placeholders for addresses
and not a pure addresses, so we need to read data pointed by
ROM symbols instead of using those as pure addresses.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-04-24 09:35:58 -07:00
Petro Karashchenko
d50ec662be arch/risc-v/esp32c3: Change the linker generated symbols from uint32_t to uint8_t *
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-04-24 09:35:58 -07:00
chao an
b8780fe906 arch/arm: relax compiler check for workaround with "GCC 12.2"
1. relax compiler check for workaround with "GCC 12.2"
2. export GCCVER to environment

Signed-off-by: chao an <anchao@xiaomi.com>
2023-04-24 19:00:52 +03:00
zhangyuan21
d7de93f906 arch/arm: Resolving warnings for assembly instructions
arm/arm_saveusercontext.S:61: Warning: duplicated register (r14) in register list

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-24 23:49:33 +08:00
Xiang Xiao
51dc67ad5f fs: Add g_ prefix for all global file_operations instances
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-04-24 16:13:29 +02:00
Huang Qi
3d3a86ae53 arch/sim: Move up_textheap_xxx to common place
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-04-24 19:37:15 +08:00
Huang Qi
97f8817d6b arch/sim: Implement host_freeheap for windows
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-04-24 19:37:15 +08:00
Huang Qi
70395f49b2 arch/sim: Implement text heap
If CONFIG_MM_CUSTOMIZE_MANAGER enabled on sim, malloc/mmap is bypassed to glibc, so the memory allocated without execution permisson.

For this case, CONFIG_ARCH_USE_TEXT_HEAP can be used.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2023-04-24 10:29:20 +08:00
YAMAMOTO Takashi
0066bf80d2 esp32: enable LIBC_ARCH_ATOMIC
fixes a build issue in https://github.com/apache/nuttx-apps/pull/1723
2023-04-24 10:12:57 +08:00
hujun5
6063c0516e cpu: in SMP pthread_cancel occasionally deadlock
In smp when cpu0 calls up_cpu_resume to release the cpu1 lock, another locked cpu1 did not execute immediately,
and soon cpu0 called up_cpu_resume again, now cpu1 unable to respond to the interrupt at this time, resulting in a deadlock.
Our solution is to restore cpu1 execution from asynchronous to synchronous to ensure that cpu1 is restored.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-04-23 23:33:09 +08:00
zhanghongyu
50488ac8f3 sim: multi netdevice forward issue when ll_guardsize not 14
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2023-04-23 10:37:50 +03:00
zhanghongyu
37644c8818 Revert "sim: multi netdevice forward issue when ll_guardsize not 14"
This reverts commit a69c6c1dac.
2023-04-23 10:37:50 +03:00
raiden00pl
d416ead27c arch/nrf52: reimplement I-Cache control operations in nrf52_start.c 2023-04-22 01:42:01 +08:00
raiden00pl
c70c178a7d arch/nrf52: nvmc and flash should depends on ALLOW_BSD_COMPONENTS=y 2023-04-22 01:42:01 +08:00
zhanghongyu
a69c6c1dac sim: multi netdevice forward issue when ll_guardsize not 14
Signed-off-by: zhanghongyu <zhanghongyu@xiaomi.com>
2023-04-22 01:41:01 +08:00
Zhe Weng
f21742899f net/netdev: Use upper half of netdev to simplify sim driver
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
2023-04-22 01:41:01 +08:00
Stuart Ianna
4cae98674d litex: Support for kernel build with vexriscv-smp. 2023-04-22 01:40:32 +08:00
qinwei1
c4f3f8801f arm64: Support for FPU profiling with procfs
Summary:

   To reduce the count of FPU context switching will result at a
performance improve with system. it need to balance between
the using of FPU and counts of FPU trap
   the PR submit a base method to see performance counts for
the FPU with NuttX procfs
   Please read README.txt at chapter of FPU Support and Performance
for more information

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
2023-04-22 01:38:21 +08:00
raiden00pl
bd9bfa9302 arch/nrf53: add RPMSG HCI controller support 2023-04-22 01:37:24 +08:00
Fotis Panagiotopoulos
873abcb9ab stm32_eth: Added error handling for abnormal interrupts. 2023-04-22 01:30:48 +08:00
Lucas Saavedra Vaz
bdfe31e850 boards/xtensa/esp32: Add ESP32-PICO-KIT support 2023-04-22 01:23:13 +08:00
zhangyuan21
dfcba925e7 arch/arm64: add cache enable and disable function
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:22:04 +08:00
zhangyuan21
652fc7648e arch/arm64: Fixed error in getting cache size when there was no mmu
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:22:04 +08:00
raiden00pl
cc7826df4d arch/nrf52: add QSPI support 2023-04-22 01:12:27 +08:00
zhangyuan21
41f83a0271 arch/arm64: change up_saveusercontext to assembly code
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:11:00 +08:00
zhangyuan21
1e726a914a arch/arm: change up_saveusercontext to assembly code
minidump will backtrace failure when use C code to save user context,
because the stack push operation in C code can disrupt the stack information.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-22 01:11:00 +08:00
hujun5
ab0b3336c4 arch/arm64:Suppot tickless mode
1 Similar to Linux and zephyr, all implementations are in arm64_arch_timer.c

2 Arm64 tickless is turned off by default. If it needs to be turned on, you need to configure the switch CONFIG_SCHED_TICKLESS ON

3 The implementation strategy for tick/tickless is to use the timer inside the CPU and implement the timer driver based on the ARCH_TIMER framework.

4 We implemented tick_* Callback functions to adapt to the driven interface to avoid time format conversion overhead

5 In arm64_tick_cancel func,The remaining time that is not used, so this value can be ignored without reading the corresponding register to obtain the remaining cycles

6 Currently, tick/tickless can takes effect in SMP and non SMP mode, ostest can pass.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-04-22 01:08:04 +08:00
David Sidrane
ac6ad45045 stm32l5:pinmap Add suffix to all pins and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings and
   all pins should have had suffixes to allow any pins attributes to
   be set. This is board dependent.

   This change adds CONFIG_STM32L5_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps with suffixes.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, CONFIG_STM32L5_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set CONFIG_STM32L5_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
7e48b58993 stm32wb:pinmap Add suffix to all pins and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings and
   all pins should have had suffixes to allow any pins attributes to
   be set. This is board dependent.

   This change adds CONFIG_STM32WB_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps with suffixes.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, CONFIG_STM32WB_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set CONFIG_STM32WB_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
a8093281c4 stm32f0l0g0:stm32f0{3|5|7|9}x_pinmap & stm32g0_pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32F0G0L0_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, CONFIG_STM32F0G0L0_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set CONFIG_STM32F0G0L0_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
77cf6ce273 stm32l4:stm32l4x{3|4|5|6|r}xx_pinmap pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32L4_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, CONFIG_STM32L4_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set CONFIG_STM32L4_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
1ece250b18 stm32:stm32f10{0|2|3{c|r|v|z}|5{r|v}|7v}_pinmap refactor
replace all GPIO_MODE_xxMHz with GPIO_MODE_2MHz provide GPIO_ADJUST_MODE
    and add legacy pinmap

    For the stm32F1 pinmaps should not have contained GPIO_MODE_50MHz settings
    on all pins. Speed is board dependent.

    This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
    lazy migration to using pinmaps that can have the GPIO_MODE_xxMHz set.

    The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
    The tools will take a board.h, and use all the defconfigs with the legacy
    pinmap and output the required changes that one needs to make to a board.h
    file.

    Eventually, CONFIG_STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
    pinmaps removed from NuttX.

    Any new boards added should set CONFIG_STM32_USE_LEGACY_PINMAP=n and
    fully define the pins in board.hf1
2023-04-19 09:58:11 +02:00
David Sidrane
ee6fb7880b stm32:stm32l15xxx pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
5d025d5d50 stm32:stm32g4xx{c|k|r|m|v|q} pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
98cd82f905 stm32:stm32f3{0|3|7}xxx pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
35258a26c0 stm32:stm32f20xxx pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
39c5931462 stm32:f4/f412 pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
1ce84fff01 stm32f7:pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
   This is board dependent.

   This change adds CONFIG_STM32F7_USE_LEGACY_PINMAP to allow for
   lazy migration to using pinmaps without speeds.

   The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
   The tools will take a board.h file and a legacy pinmap and outut the required
   changes that one needs to make to a board.h file.

   Eventually, STM32F7_USE_LEGACY_PINMAP will be deprecated and the legacy
   pinmaps removed from NuttX.

   Any new boards added should set STM32F7_USE_LEGACY_PINMAP=n and
   fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
14a0e08386 stm32h7:pinmap Remove GPIO_SPEED_xxx and add legacy pinmap
Pinmaps should not have contained GPIO_SPEED_xxx settings.
  This is board dependent.

  This change adds CONFIG_STM32H7_USE_LEGACY_PINMAP to allow for
  lazy migration to using pinmaps without speeds.

  The work required to do this can be aided by running tools/stm32_pinmap_tool.py.
  The tools will take a board.h file and a legacy pinmap and outut the required
  changes that one needs to make to a board.h file.

  Eventually, STM32H7_USE_LEGACY_PINMAP will be deprecated and the legacy
  pinmaps removed from NuttX.

  Any new boards added should set STM32H7_USE_LEGACY_PINMAP=n and
  fully define the pins in board.h
2023-04-19 09:58:11 +02:00
David Sidrane
c5f7620c42 stm32u5:stm32u585xx_pinmap Fix typo 2023-04-19 09:58:11 +02:00
David Sidrane
7e171da63f stm32wl5:pinmap Fix typo 2023-04-19 09:58:11 +02:00
zhangyuan21
c00498c164 arch/arm: update running task when context switch occurred
The text describes an issue related to the running task in code.
The running task is only used when calling the _assert function
to indicate the task that was running before an exception occurred.
However, the current code only updates the running task during
irq_dispatch, which is suitable for ARM-M architecture but not
for ARM-A or ARM-R architecture, because their context switches
are not done through irq handler. Therefore, if the following
process is followed, the value of the running task will be incorrect:

1. task1 is running, this_task()=task1
2. do_irq is executed, setting running task()=task1
3. task1 switches to task2
4. task2 is running and generates a data abort
5. In the data abort, the _assert function is called,
   and the running task obtained is still task1, but
   the actual task that generated the exception is task2.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 10:14:05 +09:00
chao an
899be58905 sim/win/hostfs: set O_BINARY for windows hostfs as default
Since the initial default setting in MSVC is text mode ( O_TEXT ):

https://learn.microsoft.com/en-us/cpp/c-runtime-library/text-and-binary-mode-file-i-o?view=msvc-170

In order to unify the translation behavior with unix,
1. set O_BINARY for hostfs as default
2. enable default text mode if the application specifies flag O_TEXT

Signed-off-by: chao an <anchao@xiaomi.com>
2023-04-19 02:55:15 +08:00
zhangyuan21
f5f0af4f9c arch/arm64: fixed backtrace skip calc error
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
2c599bb9e6 arch/arm64: call PANIC in arm64_fatal_error
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
zhangyuan21
e4ae2b48b8 arch/arm64: Obtaining the correct fp pointer
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-19 02:53:02 +08:00
chao an
49c863f238 sim/win/hostuart: only read key event from console
This commit will detect input events and filter out events(mouse/window/etc) other than key

Signed-off-by: chao an <anchao@xiaomi.com>
2023-04-19 02:52:16 +08:00
Dong Heng
45bba6e761 xtensa/esp32: ESP32 not use IMEM in user heap mode 2023-04-18 11:03:55 -03:00
yinshengkai
b705d9b1d5 sim: switch working directory
If this option is enabled, the working path of nuttx will be modified to the folder where the nuttx file is located.

Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-04-17 16:48:52 +08:00
raiden00pl
642358e68f stm32h7/rcc: make VOS0 configurable from board.h also for stm32h7x7xx
Over-drive can be forced to a given state by adding define to the
board.h configuration file:

   #define STM32_VOS_OVERDRIVE 1 - force over-drive enabled,
   #define STM32_VOS_OVERDRIVE 0 - force over-drive disabled,
   #undef STM32_VOS_OVERDRIVE    - autoselect over-drive by the default RCC logic
2023-04-17 04:23:40 -04:00
raiden00pl
876b7a5e8e stm32h7/rcc: make VOS0 configurable from board.h
It seems that over-drive is not required for ULPI but it can be a workaround solution for boards with poor signal integration.
Higher core voltage means faster clock signal edges, which may be sufficient to synchronize the high-speed clock and data on poorly designed boards.

Over-drive can be forced to a given state by adding define to the
board.h configuration file:

   #define STM32_VOS_OVERDRIVE 1 - force over-drive enabled,
   #define STM32_VOS_OVERDRIVE 0 - force over-drive disabled,
   #undef STM32_VOS_OVERDRIVE    - autoselect over-drive by the default RCC logic
2023-04-17 04:23:40 -04:00
Ville Juven
b982c1747b sched/addrenv: Miscellaneous clean-up and fixes
- Remove the temporary "saved" variable when temporarily changing MMU
  mappings to access another process's memory. The fact that it has an
  address environment is enough to make the choice
- Restore nxflat_addrenv_restore-macro. It was accidentally lost when
  the address environment handling was re-factored.
2023-04-15 13:21:48 +09:00
Tiago Medicci Serrano
869aee6a78 xtensa/sigdeliver: fix signal deliver when task is running
The Inter-Processor Interrupt that pauses the other CPU generates
a level-1 interrupt which sets the PS.EXCM. This level-1 interrupt
is treated as an Exception and the bit PS.EXCM bit is automatically
reset on return from Exception. However, this is not the case here
because we are changing the execution to the signal trampoline.
Restoring the PS register with the PS.EXCM bit set would cause any
other exception to deviate execution to the DEC (double exception
vector), avoiding it to be treated correctly. According to the
xtensa ISA: "The process of taking an interrupt does not clear
the interrupt request. The process does set PS.EXCM to 1, which
disables level-1 interrupts in the interrupt handler. Typically,
the PS.EXCM is reset to 0 by the handler, after it has set up the
stack frame and masked the interrupt." Clean the saved PS.EXCM to
1) avoid an exception from being properly treated and 2) avoid
interrupts to be masked while delivering the signal.
2023-04-15 08:19:30 +09:00
chenwen@espressif.com
8df0a4d9ef xtensa/esp32: Add support for universal mac addresses
Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
2023-04-13 09:43:30 -03:00
chao an
3f05df3fbb sim/win/hosttime: calculate sec/ms independently to avoid overflow
In the previous implementation, PerformanceCounter would cause overflow
after running for a long time, This commit will separate the calculation
of the sec/ms part to avoid this issue, Reference:

https://github.com/cygwin/cygwin/blob/main/winsup/cygwin/clock.cc#L194-L217

Signed-off-by: chao an <anchao@xiaomi.com>
2023-04-12 08:38:34 +02:00
zhangyuan21
024b13f3ed arch/arm: enable eoimode only select CONFIG_XXX_GIC_EOIMODE
On a GICv2 implementation, setting GICC_CTLR.EOImode to 1 separates
the priority drop and interrupt deactivation operations.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-11 08:54:45 +02:00
zhangyuan21
c239d19df0 nuttx: add more dependent header file
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-04-11 09:13:32 +03:00
wangming9
a7fc26124d arch/arm64: the arm64 perf interface supports pmu
Summary:
- Support arm64 pmu api, Currently only the cycle counter function is supported.
- Using ARM64 PMU hardware capability to implement perf interface, modify all
  perf interface related code.
- Support for pmu init under smp.

Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
wangming9
75760a9fdb arch/arm64: Adds custom chip option
Signed-off-by: wangming9 <wangming9@xiaomi.com>
2023-04-10 16:23:49 -03:00
raiden00pl
5e5fcd8076 fix copy-paste errors for d356ad633f 2023-04-10 03:21:36 -07:00
Petro Karashchenko
665a8e5b93 arch/arm/samv7: fix operation of TC8 and TC11
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-04-07 12:28:45 -03:00
Petro Karashchenko
4f3faded71 arch/arm/samv7: fix comment in freerun timer
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2023-04-07 12:28:45 -03:00
Gustavo Henrique Nihei
8e83379b84 risc-v/espressif: Initialize HR Timer where it is required
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
2023-04-07 12:27:56 -03:00