Driver update
* drivers/mtd/Make.defs: Add MTD driver for QuadSPI-based Winbond NOR FLASH
* stm32l4/stm32l4_qspi.c: the "QSPI_DMA_PRIO" has been defined above
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards/arm/stm32h7/stm32h747i-disco: Remove references to nucleo in the stm32h747i-disco board.
arch/arm/include/stm32h7, arch/arm/src/stm32h7, and boards/arm/stm32h7/stm32h747i-disco: Add support for the STM32H747I-DISCO board.
1) Operational issue
TC (Transmission complete) and TDRE (TX Buffer Empty) were transposed in imxrt_serial.c. The end result was that for unoptimised code everything worked fine, but optimised code got itself into a real mess and continually fired interrupts. The patch attached fixes this. This one would have been found much more quickly if this particular board had supported SWO :-/
2) Startup issue
There are a number of chip errata that apply to the 1052 first revision (A-suffix) that don't apply to the second (B-suffix). Those got me for a while and it's important to use an EVK_B_ dev board if you're suffering stability problems with this particular chip. However, even with that resolved with either optimised or unoptimised code when there is no SNVS (Battery Backup) power and the power is switched on the CPU appears to boot but gets stuck with timer interrupts not being generated. The CPU is running and it will execute linear code. I have determined this by putting an 'imxrt_lowputc('A'+irq)' into up_doirq. For the non-running case the output looks like this;
LLLL
this implies 4 0x0b interrupts have been generated, and nothing else. If I hit keys on the keyboard I get 'e' in the flow. 0x0b is the SVC instruction and is the mechanism by which NuttX handles task switching. 'e' is 0x24, which corresponds to the LPUART1 interrupt. Other than these, the system does not respond further but is happily in the idle loop. In this circumstance if you hit SW2 on the EVKB board though the logjam 'unjams' and normal service is established, output now looks like;
LLLLPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPLPP ...etc.
Where 'P' is 0x0f (the SYSTICK interrupt)....this is what _should_ be happening so; SYSTICK starts up after SW2 has been pressed.
From this point on everything works correctly and you can reboot the CPU, put new code into it or do whatever you wish, **provided power is not cycled off**. If power is cycled off then return to the top and go through the process again.
When there is SNVS power to the CPU then power can be switched on and off as you wish, and the CPU will boot correctly. This has been determined by putting 3V onto J6.
I think we are probably doing something naughty with the way we are starting the clocks to the timers. There are certainly some restrictions on imxrt clock manipulation which we have studiously avoided. I am investigating further and have some potential patches but even if I find the root cause it should not be included in 8.2 as the change could be disruptive.
https://github.com/zephyrproject-rtos/zephyr/pull/8535/commits: "The imxrt1050 is configured to use SYSTICK for the kernel timer, but SYSTICK cannot wake up the soc from low-power modes. Disable low-power modes on this soc until we have support for an alternative timer."
"This fixes k_sleep on the EVKB version of the mimxrt1050_evk board. An earlier version of the board (EVK, not EVKB), had A0 silicon which by default did not enter low-power mode on a wfi."
This patch reverts the WFI enable for further investigation post 8.2. With this patch in place together with the previous one my system is fully stable(*), just drinking a bit more power than I'd like.
(1) unifies the iomux definitions - previously some pins had them, and some didn't. This effectively made it impossible to use the pinmuxes without editing the header file in the standard distribution tree.
(2) unifies the pin definitions so that every pin now has a suffix. This makes it *much* easier to see when a pin is in use in your code, because it will always have a definition in your board.h file.
For anyone who is already using this CPU, a couple of small changes are needed to existing code;
In respect of (1) add IOMUX decorators to your pin definitions. You will find defaults in haardware/imxrt_iomux.h. Every pin should have a IOMUX decorator and in general the defaults should be OK. So while previously in your board.h file you might have had;
You will now have;
In respect of (2) you will need to add selectors for any function that previously only had one pinning option. There aren't many of those but LPUART1 is a good example. That just means adding into your board.h something like;
STM32H7:Set the BBSRAM memory range to non-cacheable.
* armv7-m:mpu add user peripheral helper
* stm32h7:BBSRAM Exclude BBSRAM from cacheable when CONFIG_ARMV7M_DCACHE
ST placed the STM32H7 BBSRAM in the SRAM default memory region
which is cacheable. This commit sets the BBSRAM memory range
to non-cacheable.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/tiva/common/tiva_flash.c: Fix several mistakes in
tiva_write() but note that this function needs more work. (1) Fix wrong
use of && when & was intended. (2) Add compile- time warning directive
because according to this function's interface, it is supposed to
support unaligned writes and/or writes of arbitrary numbers of bytes to
FLASH. However, this function does NOT support that at this time. This
needs to be fixed. (3) Fix wrong preprocessor conditional. Was written
to use the 32-word write buffer only for TM4C1294NCPDT. This buffer is
available on all TM4C123 and TM4C129 parts. Now conditioned upon
CONFIG_ARCH_CHIP_TM4C123 or CONFIG_ARCH_CHIP_TM4C129. (4) Add comments
to document the intent of the above preprocessor logic.
stm32l4_otgfs: enable OTGFS for STM32L4+ series
The OTGFS peripheral on stm32l4x6 and stm32l4rxxx reference manual is
exactly the same. This patch also adds missing bits and fixes errors in
stm32l4x5xx and stm32l4x6xx OTGFS register maps.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Add DMA support for STM32L4+ series
* Add DMA support for STM32L4+
* stm32l4xrxx_rcc: enable "Range 1 boost" mode if any PLL freq above 80 Mhz
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards: cxd56xx: spresense: cleanup and new defconfig
* arch: cxd56xx: remove NVIC_SYSH redefinition
The NVIC_SYSH is already defined in nvicpri.h
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: configs: enable SPRESENSE_EXTENSION
Enable high current mode for the Spresense Extension board on all examples
that have SDCARD support
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: ifdef SDCARD_TXS02612
The SD Card TXS02612 port expander is hosted on the Extension board and
should not be enabled if the extension board is not prezent.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: configs: increase MQ_MAXMSGSIZE
This change is needed by the display driver on spresense platform
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: spresense: config: add lcd examples defconfig
This is a configuration for the basic nx examples
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards: cxd56xx: spresense: add board_timerhook function
* boards: cxd56xx: spresense: add board_timerhook function
in preparation for SDK we muts have a weak board_timerhook function
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* drivers: usbhost: add missing endif
By accident an endif was missing.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: audio: add build barrier
The audio implementation should not be beuilt if the config
CONFIG_CXD56_AUDIO is not set.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch:arm:cxd56xx: add ge2d.h header
The header is used by imageproc.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards: arm: cxd56xx: audio: add power_control and audio_tone_generator
* boards: arm: cxd56xx: audio: add power_control
Add a simeple way to control the audio power for userspace apps
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: audio: add audio_tone_generator
Add a simple way to control the audio buzzer with defined frequency
for userspace apps
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/stm32f0l0g0: Pinmap TIM1 GPIOs available for STM32G0
arch/arm/src/stm32f0l0g0: Add TIM driver lowerhalf
arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c: Handle 32-bit overflow on some calculations.
arch: armv7-m: Fix a deadlock in up_sigdeliver() in SMP mode.
In previous implementation, up_disable_irq() was called before
recovering local context. However, I noticed a deadlock happens
in the following situation. For example, if up_sigdevliver() is
in progress on CPU0 and CPU1 has called up_cpu_paused to CPU0,
hence g_cpu_irqlock has been locked by CPU1, in this case,
we would see a deadlock in later call of enter_critical_section()
to restore irqcount.
To avoid this situation, we need to call enter_critical_section()
to break the deadlock.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Spresense smp
* arch: arm: Add ARCH_GLOBAL_IRQDISABLE to ARCH_CHIP_CXD56XX in Kconfig
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Make fpuconfg() public in cxd56_start.c
NOTE: fpuconfig() is called in both cxd56_start.c and cxd56_cpustart.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Add support for SMP
NOTE: To run cxd56xx in SMP mode, new boot loader which will be
released later must be used.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch: arm: cxd56xx: Add irq routing for SMP in cxd56_irq.c
NOTE: In cxd56xx, each external interrupt controller can be
accessed from a local APP_DSP (Cortex-M4F) only. This commit
supports IRQ routing for SMP by calling up_send_irqreq() in
both up_enable_irq() and up_disable_irq().
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* boards: spresense: Add smp configuration
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
cxd56xx: various fixes
* arch: arm: cxd56xx: Support to set any i2c frequency
This commit supports to be able to set the i2c frequency other than just
100 or 400 Hz.
* arch: arm: cxd56xx: Enable SD clock during access to SD card
- Improve GNSS low sensitivity with SD card inserted
- Reduce power consumption by stopping SD clock
* arch: arm: cxd56xx: Do PANIC() when cpu rx fifo is overflow
If CPU Rx FIFO is overflow, it's fatal error for system. In such a case,
this commit changes to allow the user to notice by calling PANIC() for
debuggability enhancement.
* arch: arm: cxd56xx: Fix compile error in sdhci debug code
* arch: arm: cxd56xx: Remove assertion in cpu tx queue
When CPU Tx queue is overflow, it returns -EAGAIN instead of assertion
to be able to retry.
* arch: arm: cxd56xx: Add configurations for cpu fifo elements
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: Fix LPADC configuration
LPADC options defined in the same symbol name, so kconfig tool
couldn't process them correctly.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: Update loader and gnssfw ver.17660
* arch: arm: cxd56xx: Fix hang-up when error interrupt occurs
Fix a problem that error interrupts are not cleared.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: Fix sdhci semaphore
Fix inital value of semaphore in sdhci drive.r
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: Treat the initial value of LNA power as off
LNA is always turned power on when GNSS is started. So it is desirable
that the initial value of the LNA power is off by default.
* boards: cxd56xx: Remove initial setting of PIN_AP_CLK
PIN_AP_CLK is used as a port selector of SDIO expander on the extension
board, and is set output low in initalizing. Therefore, this pin cannot
be used for other board. To avoid this restriction, remove this initial
operation because this pin is pulled down by default on the extension
board.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Most of the bluetooth and wifi chips appear to need external firmware, and the 43438 is no exception. Fortunately, since Cypress got involved, these are much more straightforward to obtain and are shipped as part of their SDK, which is downloadable from their website. Those firmwares are already provided as C arrays, so their names just need updating to;
const unsigned char bt_firmware_hcd -> The bt firmware array.
const int bt_firmware_len = sizeof(bt_firmware_hcd);
arch/arm/src/stm32f0l0g0/stm32g0_rcc.c: Set VOS and flash wait states properly
arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c: Renamed from arch/arm/src/stm32f0l0g0/stm32_pwr.c
arch/arm/src/stm32f0l0g0/stm32g0_pwr.c: Preliminary implementation of PWR module for STM32G0 (stm32_pwr_setvos() only)
arch/arm/include/stm32f0l0g0: add support for STM32G070CB, STM32G070KB, STM32G070RB
arch/arm/src/stm32f0l0g0: add support for STM32G070CB, STM32G070KB, STM32G070RB
stm32h7: bbsram issues causing no writes and hardfaults
* stm32_pwr:Ensure data is flushed on backup domain access changes
* stm32h7:bbsram convince compiler to perform 32 bit write
Approved-by: Gregory Nutt <gnutt@nuttx.org>
noards: arm: cxd56xx: migrate common code
* boards: arm: cxd56xx: common: move boot to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move flash to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move I2C driver to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move uid to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: move usbmsc to common
This is a common function and can be reused by all boards.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56: add SPH
The SPH is used by the ASMP implementation from the SDK.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
boards: cxd56xx: add SCU sensors (2/2)
* boards: cxd56xx: add cxd56_bh1721fvc initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bh1745nuc initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bm1383glv initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bm1422gmv initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bmi160 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_bmp280 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_kx022 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_lt1pa01 initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_rpr0521rs initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: cxd56xx: add cxd56_sensors initialization
We are adding the sensor initialization for cxd56xx boards in the
common board folder.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56: add Backup Log driver
The driver will be used to backup logs on crash.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: add crashlog driver
Add Crashlog driver with support for reset on crash
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: move gs2200m initialization
Move the board gs2200m initalization to the common board folder
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: move ili9340 initialization
Move the board ili9340 initalization to the common board folder
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: move lpm013m091a initialization
Move the board lpm013m091a initalization to the common board folder
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* boards: arm: cxd56xx: common: typo fixes
HEADER: Updates on file location
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Squashed commit of the following:
arch/arm/src/s32k1xx: Update peripheral input clocking for the way that things are done for the S32K1XX. Fix other misc. compilation/configuration issues.
arch/arm/src/s32k1xx: Clean up LPSPI and LPI2C naming for S32K1XX. Using S32K1XX clock functions to get peripheral input clock.
arch/arm/src/s32k1xx: Clone i.MXRT LPSPI and LPI2C support. i.MXRT uses the same IP as S32K1XX.
arch/arm/src/s32k1xx/s32k1xx_lowputc.c: Fix a typo that prevented LPUART1 from working.
arch/arm/src/s32k1xx/s32k1xx_periphclocks.c and related files: Fix yet another case of confusion between pre-decremented and non-decremented divider values. Enforce the rule that dividers are not decremented until the moment they are written into registers.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Fix another problem related to whether a divider is pre-decremented or not. The answer must be the divder values are never pre-decremented. They are decremented just before being written to hardware.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Clean up some bad conditional logic. Precedence of operators problem.
boards/arm/s32k1xx/s32k118evb: Add support for execution out of SRAM. This is helpful for bringup when you want to avoid putting a lethal image in FLASH.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.h: Remove crystal frequency, it is not used.
arch/arm/src/s32k1xx/s32k1xx_wdog.h: Fix a typo in a register name.i
boards/arm/s32k1xx/s32k*evb/configs/nsh/defconfig: Create Motorola SREC output format.
boards/arm/s32k1xx/s32k118evb/include/board.h: Add LPUART0 pin disambiguation.
arch/arm/src/s32k1xx/hardware: Add pin mux definitions for S32K116, 118, 142, 144, 146, and 148.
arch/arm/src/s32k1xx/s32k1xx_pin.c and .h: Add support for PIDR register that disables a gneral purpose pin from acting as an input.
arch/arm/src/s32k1xx/s32k1xx_pin.c and .h: The device does not support slew rate controls or open drain (on all the pins). Only pins that are configured for a protocol that requires open-drain (e.g;, LPI2C, LPUART single-wire) will work in open-drain mode.
arch/arm/src/s32k1xx/: Add logic to look up the peripheral clock frequency. Fix baud calcuation logic in s32k1xx_lowputc.c: In no longer tries to enable clocking. That must be done with board logic. Now gets the peripheral functional clock frequency to determine the baud rate.
arch/arm/src/s32k1xx: Add peripheral feature arrays.
Finishes peripheral clock initialization:
arch/arm/src/s32k1xx/s32k11x/s32k11x_clockmapping.c
arch/arm/src/s32k1xx/s32k14x/s32k14x_clockmapping.c
Provide MCU-specific mapping of clock names to PCC control registers.
boards/arm/s32k1xx/s32k118evb/src/s32k118_periphclocks.c
Provides initial clocking for for the S32K118EVB
arch/arm/src/s32k1xx/s32k1xx_periphclocks.c: Add logic to initialize peripheral clocking.
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Add SIM clock configuration.
stm32h7 RTC and friends support
* stm32h7:Removed f7 in file path
* stm32f7:Fix overwritten IRQ enabled
System boot order calls clock_initialize then up_initalize.
clock_initialize was setting up the alarm IRQ
up_initalize is initializing the NVIC.
This most likely worked in the past due to a bug in the
NVIC init code that failed to clear the Interrupt enables.
That was fixed in 510b0f7e arch/arm/src: Correct all ARMv7-M
architectures. Interrupts were not be disabled correctly
on power up.
* stm32h7:Ported over F7 RTC
* nucleo-h743zi:Add RTC
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c: Finishes the implementation of the core clock configuration logic.
arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h: Add SMC register definition header file.
arch/arm/src/s32k1xx: Bring in GPIO logic from Kinetis. Looks like the same IP.
serial single-wire: add possibility to specify pull-up instead of open drain
Approved-by: David Sidrane <david.sidrane@nscdg.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Master
* Revert "Merged in yanqil-br/feature-multi_chan_pwm (pull request #973)"
This reverts commit aef0e0b538.
* arch/arm/src/{stm32/stm32f7/stm32h7/stm32l4}/stm32_pwm.c: configure multi-channel duty only if channel specified. This allows you to update duty cycle for a single channel
* nucleo-f303re/configs: add basic NSH configuration
* nucleo-f303re/configs/pwm: enable console on UART2 and set entry point to nsh_main
Approved-by: Gregory Nutt <gnutt@nuttx.org>
stm32f7: USART1_RXDMA is dependent on STM32F7_DMA2 not STM32F7_DMA1
Approved-by: David Sidrane <david.sidrane@nscdg.com>
Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/tiva/Kconfig:
Remove EXPERIMENTAL dependency on TIVA_TIMER16_PWM.
arch/arm/src/tiva/common/tiva_timerlib.c:
Fix wrong 32/16-bit ifdef checks.
Add tiva_pwm16_sel_event() to choose GPTMCTL.TnEVENT value.
Implement tiva_pwm_mode16().
tiva_timer16_setinterval(): Fix wrong check for TIMER16_MODE_ONESHOT
and TIMER16_MODE_PERIODIC. Was comparing to config->cmn.mode
which can never have those values. This prevented interrupts being
enabled. Compare to timer->mode instead.
Add tiva_timer16pwm_setperiodduty() to set initial period, duty cycle,
and enable interrupts if requested in GPTM peripheral. Interrupts
are not enabled in NVIC until tiva_timer16_start() is called.
Add tiva_timer16pwm_setduty() to update duty cycle at any time.
arch/arm/src/tiva/hardware/lm/lm3s_timer.h,
arch/arm/src/tiva/hardware/lm/lm4f_timer.h,
arch/arm/src/tiva/hardware/tm4c/tm4c123_timer.h,
arch/arm/src/tiva/hardware/tm4c/tm4c129_timer.h:
Add missing defines; make surrounding defines consistent.
arch/arm/src/tiva/tiva_timer.h:
Add new TIMER_FLAG_* configuration flags to enable configuring the
16-bit PWM feature. Extend type of "flags" in tiva_timer32config_s
and tiva_timer16config_s from 8- to 32-bits to allow more flags.
If we are using the BASEPRI register to disable interrupts, then the answer is that we must disable ONLY the "normal interrupts". That is because we cannot disable SVCALL interrupts and we cannot permit SVCAll interrupts running at a higher priority than the high priority interrupts (otherwise, they will introduce jitter in the high priority interrupt response time.)
Hence, if you need to disable the high priority interrupt, you will have to disable the interrupt either at the peripheral that generates the interrupt or at the NVIC. Disabling global interrupts via the BASEPRI register cannot effect high priority interrupts.
arch/arm/src/tiva/common/tiva_timerlib.c:
* tiva_gptm_configure() and tiva_gptm_release(): Fix error: Was calling
tiva_emac_periphrdy() instead of tiva_gptm_periphrdy().
arch/arm/src/tiva/tiva_timer.h:
* Fix error in "abcde" description of bit flag defines.
kinetis:i2c transfer ensure correct result returned
kinetis_i2c_transfer released the mutex then fetched
the state, this resulted in returning the correct
results.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Move boards to boards folder
* boards: rename configs folder to boards
This is the proposed layout after the change:
boards: - folder containing board folders
<board>: - name of each board
drivers: - extra drivers specific for platform
include: - header files for the boars
scripts: - extra scripts specific for platform
src: - board specific code
tools: - extra tools specific for platform
<config>: - board specific configuration(s)
Note:
<xxx> names are dependent on platform
This is a logical change to aim to the arch layout but this is a
huge change it should be done in several steps to lower the risk.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Kconfig: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Makefile: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Makefile.*: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* Make.defs: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .sh: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .mk: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .c & .h: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* .bat: replace configs with boards
The change is needed after the path change
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Rationale: TM4C1294NC is ambiguous:
TM4C1294NCPDT is a 128-TQFP
TM4C1294NCZAD is a 212-NFBGA
The TM4C1294NC part currently supported by NuttX is the TM4C1294NCPDT used on the TI EK-TM4C1294XL "Connected LaunchPad" (see configs/tm4c1294-launchpad). To ensure the correct part is fully specified, this commit updates all TM4C1294NC identifiers to TM4C1294NCPDT.
Rename:
CONFIG_ARCH_CHIP_TM4C1294NC to CONFIG_ARCH_CHIP_TM4C1294NCPDT
ARCH_CHIP_TM4C1294NC to ARCH_CHIP_TM4C1294NCPDT
TM4C1294NC to TM4C1294NCPDT
Rationale: In terms of firmware programming, there is no functional difference between these parts:
TM4C123GH6PMI7
TM4C123GH6PMI7R
TM4C123GH6PMT7
TM4C123GH6PMT7R
From a programming standpoint, all of the above parts are TM4C123GH6PM, which means it doesn't make sense to differentiate between PM and PMI. (The PM means 64-LQFP. The I means temperature range -40C to +85C. It could be T meaning -40C to +105C. The R means it ships in Tape and Reel packaging as opposed to Tray.)
arch/arm/include/tiva/chip.h:
arch/arm/include/tiva/tm4c_irq.h:
arch/arm/src/tiva/hardware/lm/lm3s_flash.h:
arch/arm/src/tiva/hardware/tm4c/tm4c_pinmap.h:
configs/tm4c123g-launchpad/README.txt:
configs/tm4c123g-launchpad/nsh/defconfig:
Rename: CONFIG_ARCH_CHIP_TM4C123GH6PMI to CONFIG_ARCH_CHIP_TM4C123GH6PM
arch/arm/src/tiva/Kconfig:
configs/Kconfig:
Rename: ARCH_CHIP_TM4C123GH6PMI to ARCH_CHIP_TM4C123GH6PM
arch/arm/src/tiva/hardware/tm4c/tm4c_memorymap.h:
Rename: CONFIG_ARCH_CHIP_TM4C123GH6PMI to CONFIG_ARCH_CHIP_TM4C123GH6PM
Remove redundant Peripheral Base Addresses section. There were two identical copies, one for CONFIG_ARCH_CHIP_TM4C123GH6PMI and another for CONFIG_ARCH_CHIP_TM4C123GH6PM.
Testing of the WiFi is minimal so far but functionality is proven. I'm specifically not happy that the driver doesn't recover elegantly from a DMA data checksum failure, but that is an issue that can be dealt with in due course ... I'm trying to get the rest of the interfaces fleshed out and the hardware proven so it can go for pre-production build. I _think_ there's only Bluetooth and USB-device left to implement now.
- Fix for mx25rxx driver as it does not work properly
- Add mx25rxx memory chip & smartfs support in b-l475e-iot01a/nsh config
- Update smartfs smart_scan() function
stm32f7: Fixes bad preprocessor logic preventing USB OTG HS to work when used without external ULPI.
Approved-by: David Sidrane <david.sidrane@nscdg.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Add support for LPC40xx family chips
* Corrected a few peripheral definitions and pin functions for the LPC17xx family.
Added configuration options, chip definitions, and additional pin functions for the LPC40xx family.
Added board configurations for Embedded Artists LPC4088 Quickstart board and LPC4088 Developer's kit. These configurations are still something of a work in progress. In particular, the LCD functionality is untested.
* First pass rename in *.c and *.h files.
* Renamed LPC17XX to LPC17XX_40XX in config files
* Rplaced LPC17xx with LPC17xx/LPC40xx in .c files
* Replaced LPC17xx with LPC17xx/LPC40xx in .h files
* Updated some documentation
* Working on moving directories
* moved arch/arm/src/lpc17xx and arch/arm/include/lpc17xx to lpc17xx_40xx
* Renamed LPC17_* constants / configuration options to LPC17_40_*
* Updated chip family name defines
* Renamed some chip-specific files
* Updated references to renamed files
* Updated references to lpc17_ to lpc17_40_
* Renamed source files from lpc17_* to lpc17_40_*
* Clean up white space
Approved-by: Gregory Nutt <gnutt@nuttx.org>
drivers/lcd/tda19988.c: Now uses the new common videomode structure of include/nuttx/video/videomode.h as do other video components.
video/, include/nuttx/video/videomode.h: Separate EDID and from videomode managment. They really are separate things.
back at physical address 0x2007C000 and 0x20080000 (i.e. right below and right
above a 512 KiB boundary). Memory from those two blocks is considered
continuous when assigned to a heap.
In the protected build mode, when the memory protection unit is used, though,
it must be split into two MPU regions. This is because MPU regions must be
naturally aligned, and the 32KiB continuous address space of the two 16KiB AHB
SRAM blocks does not start at an address divisible by 32KiB.
The only other configurations that use protected build mode on lpc17xx are
currently open1788/knsh and open1788/knxterm. The LPC1788 has the AHB SRAM
blocks mapped more sanely (from an MPU region point of view), which is
probably why no problems emerged here. Both still compile with my change and
other than wasting an MPU region (which would otherwise remain unused) should
work fine. That said, I have no hardware to confirm.
arch/arm/src/am335x: Add logic to map the framebuffer to a non-cached, non-buffered memory region.
arch/arm/src/am335x: Remove struct am335x_fbinfo_s. Replaced with configuration settings that provide the same information.
Squashed commit of the following:
arch/arm/src/am335x/am335x_lcdc.c: LCD driver now compiles.
arch/arm/src/am335x/am335x_lcd.c: This brings the LCD driver to code complete. Have not yet attempted to compile.
arch/arm/src/am335x/am335x_edid.c: Framebuffer is pre-allocated. In verification of video mode, include a test to assure that the video mode can be supported by the pre-allocated framebuffer memory.
arch/arm/src/am335x/am335x_lcd.c: At a little bit of LCD initialization logic. There is a long way to go.
arch/arm/src/am335x/am335x_edid.c: Add am335x_lcd_videomode() which provides an alternative way of initializing the LCD controller.
arch/arm/src/am335x/am335x_edid.c: edit.h has move to include/nuttx/video.
arch/arm/src/am335x/hardware/am335x_cm.h: Fix a typo in a macro name.
arch/arm/src/am335x/am335x_edid.c: Integrate video/edid support.
arch/arm/src/am335x/am335x_edid.c: Fall back to VGA mode is not valid videomode is availabe in the EDID data.
arch/arm/src/am335x/am335x_edid.c: Fixes for a partially clean compile.
arch/arm/src/am335x/am335x_edid.c: Add basic logic to convert EDID montor descriptions into a form usable for LCD configuration.
arch/arm/src/am335x: Add framework (only) for an LCD driver. Initial commit is simply the LPC54 framebuffer driver with naming changes.
Improve gs2200m performance
* arch/arm/src/cxd56xx: Fix dma initialization in cxd56_dmac.c
up_dma_initialize() must be used instead of up_dmainitialize()
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* drivers/wireless: Introduce CONFIG_WL_GS2200M_SPI_FREQUENCY
Also, changed usleep(100) to up_udelay(100) to avoid invalid response.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/spresense/wifi: Improve performance for webserver
This commit changes followings.
1. Enable SPI DMA for both TX and RX
2. Increase SPI clock speed from 4MHz to 10MHz
3. Increase buffer size for sendfile() from 512B to 1KB
4. Enable sendfile() for webserver
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/tiva: Add a workaround for tiva with qemu
With qemu, tiva_ifup() hangs because ethernet link status can not
be set correctly. This PR is a workaround to avoid this issue.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
configs: spresense: add I2CTOOL support and extend GPIO for future use
* arch: arm: cxd56xx: add delay support
add delay support for cxd56xx chip
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* configs: spresense: register I2C busses
for development is usefull to register I2C busses when the I2CTOOL
is built
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* configs:spresense: enable GPIO interface
enable GPIO interface on spresense board
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch: arm: cxd56xx: SCU, ADC, I2C
* nuttx: configs: spresense: LEDS: fix warnings
In the initial code several errors were missed because I pushed
the dirty code.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add Sensor Control Unit (SCU)
Add Sensor Control Unit (SCU) on cxd56xx chip
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add I2C support
add I2C support on cxd56xx chip
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add ADC interface support
Add ADC interface support on cxd56xx chip
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: Use DMAC for reading sensing data
Use DMAC for reading sensing data from SCU on cxd56xx chip
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: code style sanitization
NuttX does not use Deoxygen for documentation and no file should contain Doxygen tags or Doxygen style comments.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* configs: spresense: enable I2CDEV
add enable I2CDEV for spresense board
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* configs: spresense: add notification LEDs
Add usefull diagnostic LEDs on the speresense board
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch: arm: cxd56xx: add UID support
* arch: arm: cxd56xx: add UID support
Add support to be able to read the HW UID
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* configs: spresense: enable USERLEDS
add USERLED for spresense board
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch: arm: cxd56xx: PM and PWM
* configs: spresense: add SPI configuration
add SPI configuration for spresense board
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add support for PWM
add support for PWM for cxd56xx
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* configs: spresense: enable PWM support
enable PWM support on spresense board
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add Power Management PROCFS support
the powermanager procfs support will export
/proc/pm:
clock
power
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* configs: spresense: enable powermanager procfs support
The powermanager procfs is disabled by default and need to be enabled
by the CONFIG_CXD56_PM_PROCFS option
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add timer driver
Add timer driver for cxd56xx.
NOTE
The timer allows a divider of 1, 16 and 256 options
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add Watch Dog Timer
Add Watch Dog Timer on cxd56xx
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* configs: spresense: enable timer
the platform support has been added and now we can use the timers
on spresense board.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* configs: spresense: enable WatchDog timer
The platform support has been added and now we can use the WatchDog
Timer on spresense board.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
stm32 h7 Add ADC and a few fixes for timer and Serial
* stm32h7:Fix error when SINGLEWIRE or CONFIG_STM32H7_SERIALBRK_BSDCOMPAT defined
* stm32h7:time fixed compile errors with TIM13,TIM14, TIM7
* stm32h7:Added ADC Driver
* stmh7x3:Added ADC pins to pin map
* stm32h7:Added ADC clocking
* nucleo-h743zi:Add ADC
Approved-by: Gregory Nutt <gnutt@nuttx.org>
rndis on spresense
* arch/arm/src/cxd56xx: Fix ep0 out packet handling in cxd56_usbdev.c
This change fixes to handle ep0 out packet which exceeds EP0_MAXSIZE.
For example, 76 bytes of out packet is sent from rndis host during
rndis negotiation and finally the packet is split into two out packets
(64 bytes out packet + 12 bytes out packet). To handle these packets,
actual ep0reqlen is stored during ep0 out setup stage, and if all
out packets are received, it dispatches to cxd56_ep0setup(), otherwise,
it sets up the internal USB DMA to receive remaining out packets.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/spresense: Add support for rndis configuration
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Add syscontrol for cxd56xx
* arch: arm: cxd56xx: add sysctl
Add the syscontrol implementation for cxd56xx.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: timer updates
Add the function to change the clock speed.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: cxd56_uart updates
Add pinctrl and clock ctrl functionality.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add conditional for SDHCI
The cxd56_sdhci should be built only if CONFIG_CXD56_SDIO is selected
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch: arm: cxd56xx: add Power Management support
* arch: arm: cxd56xx: add Power Management support
Add power management on the cxd56xx
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add Far API
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch: arm: cxd56xx: add support for USB and SDIO
* arch: arm: cxd56xx: add support for USB connectivity
Add basic support for USB connectivity
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add SDHCI support
We add SDHCI driver for the cxd56xx
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch: arm: cxd56xx: add Package Configuration
The CXD56xx can come in FCBGA 185 pin or WLCSP 100 pin package.
For each package we have to pick the right pin setup.
The default configuration is set to FCBGA 185 pin package
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Improvements for STM32 PWM
arch/arm/src/stm32/stm32_pwm: add support for all PWM modes
arch/arm/src/stm32/stm32_pwm: add interface to change PWM mode
arch/arm/src/stm32/stm32_pwm: refactor pwm_mode_configure()
arch/arm/src/stm32/stm32_pwm: STM32_PWM_CHANx corresponds to the timer channel and STM32_PWM_OUTx corresponds to the timer channel output
arch/arm/src/stm32/stm32_pwm: add CHAN5 and CHAN6 to PWM_TIMx_NCHANNELS
arch/arm/src/stm32/stm32_pwm: calculate the PWM_TIMx_NCHANNELS if CONFIG_STM32_PWM_MULTICHAN is selected
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Squashed commit of the following:
arch/arm: Rename include/stm32f0l0 and src/stm32f0l0 to stm32f0l0g0.
Change all occurrences of lower-case stm32f0l0 to stm32f0l0g0.
Change all occurrences of upper-case STM32F0L0 to STM32F0L0G0.
