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eaea60a575
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20161 Commits

Author SHA1 Message Date
Michael Jung
eaea60a575 armv8-m: Fix pthread_start syscall 
The 'arg' parameter is in R3, not in R2.

Signed-off-by: Michael Jung <michael.jung@secore.ly>
 2023-01-26 04:02:19 +08:00
Petro Karashchenko
be10056702 arch/arm/samv7: fix issue when AFEC1 driver failed to open second time 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2023-01-26 01:26:41 +08:00
Xiang Xiao
d7ee492fc4 board/arch: Remove FAR decorator 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-01-25 13:05:07 +02:00
Stuart Ianna
34fdc3da0d litex: Allow custom peripheral memory mapping and IRQ. 2023-01-25 14:11:06 +08:00
Xiang Xiao
43e7b13697 assert: Log the assertion expression in case of fail 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-01-24 15:00:19 -03:00
Ville Juven
9b88f8ea5c riscv/riscv_exception.c: Print the EPC value always 
The value printed by assert() cannot always be trusted to be correct,
as it relies on the stack / stack pointer not being corrupt.

The CPU register always points to the faulting instruction so print it
out in the exception handler.
 2023-01-25 00:55:07 +08:00
Stuart Ianna
f49c20d28f litex: System clock frequency selectable from Kconfig. 2023-01-24 08:20:16 +01:00
Gustavo Henrique Nihei
e77e12e145 espressif: Stabilize MCUboot support on Espressif chips 
MCUboot support is no longer behind EXPERIMENTAL for the following
chips:
- ESP32
- ESP32-S2
- ESP32-S3
- ESP32-C3

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-01-24 08:44:22 +09:00
David Sidrane
15462f3e7a s32k1xx:serial Do not use TC use TDRE & TIE 2023-01-24 06:47:21 +08:00
raiden00pl
aa7d4b40c1 stm32/foc: move the warning in the right place - should be in stm32f7 2023-01-24 00:44:41 +08:00
raiden00pl
bfdb7f8909 stm32f7,stm32/foc: support for BEMF sensing 
stm32 version tested with b-g431b-esc1
stm32f7 version not tested on HW
 2023-01-22 12:58:04 -03:00
raiden00pl
01d84408e6 stm32,stm32f7/adc: add interface to configure multi mode ADC 2023-01-22 12:58:04 -03:00
raiden00pl
f3fde0e9a8 stm32,stm32f7/foc: improve pwm_off 2023-01-22 12:58:04 -03:00
raiden00pl
bd6a0b08db stm32,stm32f7/foc: support for pwm_off() 2023-01-21 12:28:16 +08:00
Lucas Saavedra Vaz
39162ebafb arch/xtensa/esp32: Add support for RTC IRQs 2023-01-21 12:27:35 +08:00
raiden00pl
91d43edffd drivers/foc: support for BEMF sensing 2023-01-20 21:26:27 +02:00
Alan Carvalho de Assis
2bdb7c0e8d esp32s2: Add support to EFUSE 2023-01-20 15:41:13 +08:00
Alan Carvalho de Assis
adc5f52fcf esp32s3: Add support to EFUSE 2023-01-20 15:40:46 +08:00
Max Kriegleder
57034f483d esp32: fix lower half oneshot for usage with nxsched_oneshot_start 2023-01-20 15:39:47 +08:00
Jukka Laitinen
e2a7cee5ed arch/mpfs: Make selection of SBI boot or direct boot run-time configurable 
Allow bootloader to select run-time whether the payload binary is booted with
SBI or directly by jumping to entrypoint address.

- Use just one bitmask to select sbi or direct boot for each hart
- Add mpfs_set_use_sbi function to allow selecting how to boot
- Initialize the bitmask by default according to the configuration flags
- Add a header file for including the function prototypes in bootloader code

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2023-01-20 00:08:51 +08:00
Xiang Xiao
fd64e38072 build: Add STACK_USAGE(-fstack-usage) to assist the stack analysis 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-01-19 10:35:20 -03:00
Masayuki Ishikawa
dc454765fb Revert "add holder for mutex" 
This reverts commit fc176addeb.
 2023-01-19 06:04:48 +09:00
Ville Juven
0922121bc0 riscv/addrenv: Do not free physical memory for SHM area 
SHM area is just mapped memory, the physical backup is not owned by the
process, so the process must not free it.

In ARM this is already handled as the regions are destroyed one by one,
while this implementation does a page directory walk instead.
 2023-01-18 21:59:55 +08:00
David
5dbd082fad Bugfix of typo in tiva_can.c 2023-01-18 12:15:53 +01:00
Gustavo Henrique Nihei
a4c9da9280 xtensa/esp32: Fix ESP32_SPIRAM_USER_HEAP under Protected mode 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-01-18 17:41:09 +08:00
Gustavo Henrique Nihei
e451b43798 xtensa/esp32: Improve Wi-Fi driver to support MM_KERNEL_HEAP 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-01-18 17:41:09 +08:00
Gustavo Henrique Nihei
705e29fb27 xtensa/esp32: Support allocation of userspace heap into External RAM 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2023-01-18 17:41:09 +08:00
lilei19
fc176addeb add holder for mutex 
Signed-off-by: lilei19 <lilei19@xiaomi.com>
 2023-01-18 17:40:58 +08:00
Zhe Weng
1cf3147626 net/netdev: Avoid hardcoded guardsize when using d_iob 
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
 2023-01-18 14:41:07 +08:00
Dong Heng
f35f32d4ee xtensa/esp32: Fix SPI bugs 
1. Fix SPI master/slave clock init/deinit error
2. Fix SPI slave RX process error
 2023-01-18 12:23:08 +08:00
Ville Juven
201a55c7cb arm/addrenv_utils: Don't touch L1 mappings in addrenv_destroy() 
This is unnecessary, the address environment is getting wiped anyway,
there is no need to remove the L1 references because they will get
wiped when the page directory is changed
 2023-01-18 11:02:19 +08:00
Ville Juven
58b5a0412e riscv/addrenv_shm: Add missing sanity check to up_shmdt() 
A missing sanity check, make sure the last level page table actually exists
before trying to clear entries from it.
 2023-01-18 02:45:04 +08:00
anjiahao
bc30b294aa mm:add heap args to mm_malloc_size 
use malloc_size inside of where used mm_malloc_size

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
 2023-01-17 21:57:37 +08:00
dongjiuzhu1
8101978765 arch/sim: fix compile break when using mallinfo_task with custom mm manager 
/usr/bin/ld: nuttx.rel: in function `mallinfo_task':
nuttx/mm/umm_heap/umm_mallinfo.c:67: undefined reference to `mm_mallinfo_task'

Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
 2023-01-17 16:48:30 +08:00
luoyong1
a32124879d arch/arm/src/armv7-a/r: fix kconfig error of l2 cache latency 
fix the error of the config name and set latency config param bool to int

Signed-off-by: luoyong1 <luoyong1@xiaomi.com>
 2023-01-17 12:45:42 +09:00
Xiang Xiao
62c5afe655 Fix warning in file included from chip/sam_clockconfig.c:34: 
chip/sam_clockconfig.c: In function 'sam_usbclockconfig':
Error: /github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:51: error: 'regval' is used uninitialized [-Werror=uninitialized]
  135 | #define putreg32(v,a)  (*(volatile uint32_t *)(a) = (v))
      |                                                   ^
chip/sam_clockconfig.c:422:12: note: 'regval' was declared here
  422 |   uint32_t regval;
      |            ^~~~~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-01-16 18:59:44 -03:00
ligd
fedad91b0d sim/mem: don't let siwtch out when operated the host mem 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2023-01-17 01:18:03 +08:00
ligd
c08cc01c9d sim/oneshot: don't need sleep_until when open CONFIG_SIM_WALLTIME_SIGNAL 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2023-01-17 01:18:03 +08:00
Xiang Xiao
f64da13e9b libxx: Add CXX_STANDARD to select -std=c++?? 
and default to "c++17"

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-01-16 15:41:57 +02:00
TimJTi
6b4da4ad6e Ensure SFR CKTRIM register correctly set, SAMA5D2/D3 only 2023-01-16 21:40:00 +08:00
Dong Heng
118222ba46 xtensa/esp32: Partition device supports encryption mode 2023-01-16 09:55:44 -03:00
dongjiuzhu1
7cd325f3be mm/mm_heap: remove kasan in MM_ADD_BACKTRACE 
do simple copy to instead of memset and memcpy operation because
they have been instrumented, if you access the posion area,
the system will crash.

Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
 2023-01-16 20:32:17 +08:00
chao an
415a09115d boards/sim/windows: enable custom options 
1. boards/sim: enable child status
2. boards/sim/windows: enable custom options
3. sim/windows: enable hostfs

Signed-off-by: chao an <anchao@xiaomi.com>
 2023-01-16 20:30:39 +08:00
zhangyuan21
806a2a8b8d arch/armv7-ar: flush dcache when addr is not aligned with cache line 
When invalidate address is not aligned with cache line,
must align address and flush the cache line.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
 2023-01-16 16:14:32 +08:00
zhangyuan21
4bb155db64 arch/arm: add barrier instruction for cache ops 
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
 2023-01-16 16:14:32 +08:00
Xiang Xiao
f783f5c384 arch/arm: Fix typo error in cp15_cacheops.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-01-16 16:14:32 +08:00
Xiang Xiao
1ea9db4ebe Fix error: implicit declaration of function 'cp15_invalidate_icache'; did you mean 'cp15_invalidate_dcache'? 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-01-16 16:14:32 +08:00
chenrun1
c61195bcc9 arch/armv7-a & armv7-r:Add invalidate icache behavior 
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
 2023-01-16 16:14:32 +08:00
ligd
7e4c5d3daa armv7a/r: cache function should depends on CONFIG_ARCH_XCACHE 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2023-01-16 16:14:32 +08:00
Julian Oes
22fa59074f stm32h7: add SMPS PWR option for STM32H7X7 
The dual core STM32H747 / STM32H757 there is an additional option to
select SMPS rather than LDO as the power selection.

This commit adds this option to the STM32H747 config and the
stm32h7x7xx source.

Signed-off-by: Julian Oes <julian@oes.ch>
 2023-01-16 13:31:23 +08:00