7 Commits

Author SHA1 Message Date
Xiang Xiao
4e66d55a17 arch/arm: Fix the style warning
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2021-03-26 17:01:24 +01:00
Alin Jerpelea
df7bffe8fd arch: arm: armv7-r: fix nxstyle errors
Fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
2021-03-25 19:42:44 -07:00
Xiang Xiao
cde88cabcc Run codespell -w with the latest dictonary again
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2020-02-23 22:27:46 +01:00
Xiang Xiao
80277d1630
Refine the preprocessor conditional guard style (#190) 2020-01-31 19:07:39 +01:00
Xiang Xiao
64252a298f arch/: Unify the cache interface for all architectures 2019-03-19 10:37:13 -06:00
Gregory Nutt
7475712d87 ARMv7-R: Review/update cache operations 2015-12-14 12:32:32 -06:00
Gregory Nutt
5585f44b7e Add initial support for ARMv7-R architecture. Initial commit is largely a clone of ARMv7-A and needs further review 2015-12-14 08:40:38 -06:00