Commit Graph

5 Commits

Author SHA1 Message Date
Xiang Xiao
76bbed07a4 Call up_irqinitialize from irq subsystem
Call up_irqinitialize from irq subsystem to make the irq ready for use as soon as possible
2020-02-08 07:39:22 -06:00
Xiang Xiao
68951e8d72 Remove exra whitespace from files (#189)
* Remove multiple newlines at the end of files
* Remove the whitespace from the end of lines
2020-01-31 09:24:49 -06:00
Masayuki Ishikawa
4ea49c5691 Fix issues on fe310 including interrupt handling (#46)
* arch: fe310: Fix comments

* arch: fe310: Improve irq handling in fe310_serial.c

* arch: fe310: Fix initial interrupt status (mstatus)

Also, removed unnecessary up_enable_irq(FE310_IRQ_ECALLM)
2020-01-07 07:17:39 -03:00
Masayuki Ishikawa
0eb9bfa49d Merged in masayuki2009/nuttx.nuttx/fe310_with_pll (pull request #1094)
fe310 with pll

* arch: fe310: Introduce CONFIG_ARCH_CHIP_FE310_QEMU

* boards: hifive1-revb: Introduce CONFIG_ARCH_CHIP_FE310_QEMU

* arch: fe310: Add support for PLL

* boards: hifive1-revb: Increase uart0 tx buff size and add getprime app

Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-12-11 12:01:53 +00:00
Masayuki Ishikawa
7a8e9581ca Merged in masayuki2009/nuttx.nuttx/hifive1-qemu (pull request #1078)
HiFive1 with qemu

* arch: risc-v: Add include/.gitignore

* arch: risc-v: Add src/.gitignore

* arch: risc-v: Remove uncommon function prototypes in include/irq.h

* arch: risc-v: Add missing symbols and function prototypes in src/common/up_internal.h

* arch: risc-v: Add src/common/up_modifyreg32.c

* arch: risc-v: Enable include Make.dep in src/Makefile

* arch: risc-v: Fix stack coloration in common/up_createstack.c

* arch: risc-v: Add common/up_puts.c

* arch: risc-v: Add common/up_checkstack.c

* arch: rv32im: Move all logics from up_dumpstate.c to up_assert.c

    This change is same as other architectures like arm/src/armv7-m

* arch: Select ARCH_HAVE_STACKCHECK for RISC-V in Kconfig

* arch: risc-v: Add SiFive fe310 processor

    NOTE: Currently only tested with qemu

* boards: hifive1-revb: Add SiFive hifive1-revb board

    NOTE: Currently only tested with qemu

* tools: Add fe310 processor to configure.sh

Approved-by: Alan Carvalho de Assis <acassis@gmail.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
2019-11-28 20:37:24 +00:00