Both CPUs are soft-reset with a call to board_reset. This is actually a
Core Reset, so both cores and all registers are reset. The only
exception is RTC.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Summary:
- This commit adds interrupt stack for SMP
Impact:
- Affects SMP only
Testing:
- Tested with spresense:wifi_smp with CONFIG_ARCH_INTERRUPTSTACK=2048
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- The handle_irqreq() is used for remote IRQ control.
- The logic is called via IPI (Inter-Processor Interrupt)
- And the handler should handle only one request
- However, I noticed that the handler handles up to two requests
- This commit fixes this issue
Impact:
- Affects SMP cases only
Testing:
- Tested with spresense:wifi_smp
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Not all boards have an interrupt line from the phy to
the Soc. This commit allows the phy to be polled for
link status.
This may not work on all MAC/PHY combination that
have mutually exclusive link management and operating
modes. The STM32F7 and LAN8742AI do not have such a
limitation.
Summary:
- Apply the same fix for Arm SMP
Impact:
- Affects SMP only
Testing:
- Tested with esp32-core:smp (qemu)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- Apply the same fix for Arm SMP
Impact:
- Affects SMP only
Testing:
- Tested with maix-bit:smp (qemu)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Summary:
- I found an issue with up_interrupt_context() when testing.
- And finally found that up_interrupt_context() is not atomic.
- This commit fixes the issue
Impact:
- Affects SMP only
Testing:
- Tested with spresense:wifi_smp and sabre-6quad:smp (qemu)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
When executing an MRET instruction, MIE is set to MPIE.
In order to branch to up_sigdeliver() with interrupts disabled,
we need to change MPIE, not MIE.
When executing an MRET instruction, MIE is set to MPIE.
In order to branch to up_sigdeliver() with interrupts disabled,
we need to change MPIE, not MIE.
There was no error handling before and it would block on common
cases like NACK which meant that you could not use the i2ctool
to perform a scan of the bus.
This does not handle the interrupt flow which also has incomplete
error handling.
This commit corrects the following compilation error:
/usr/include/cygwin/socket.h:27:8: error: redefinition of 'struct sockaddr'
27 | struct sockaddr {
| ^~~~~~~~
In file included from /usr/include/w32api/winsock2.h:57,
from sim/up_wpcap.c:48:
/usr/include/w32api/psdk_inc/_ip_types.h:70:8: note: originally defined here
70 | struct sockaddr {
| ^~~~~~~~
In file included from /usr/include/sys/socket.h:13,
from /usr/include/cygwin/in.h:21,
from /usr/include/netinet/in.h:12,
from sim/up_wpcap.c:57:
/usr/include/cygwin/socket.h:39:8: error: redefinition of 'struct sockaddr_storage'
39 | struct sockaddr_storage {
| ^~~~~~~~~~~~~~~~
In file included from sim/up_wpcap.c:48:
/usr/include/w32api/winsock2.h:269:10: note: originally defined here
269 | struct sockaddr_storage {
| ^~~~~~~~~~~~~
The compilation was broken by a couple of recent blind, unverified changes to up_wpcap.c. Most were introduced with commit: 8ce0ff5ce4 with this change:
diff --git a/arch/sim/src/sim/up_wpcap.c b/arch/sim/src/sim/up_wpcap.c
index ef7b4b3a0c..a15421e80c 100644
--- a/arch/sim/src/sim/up_wpcap.c
+++ b/arch/sim/src/sim/up_wpcap.c
@@ -55,6 +55,8 @@
#include <netinet/in.h>
+#include "up_internal.h"
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
up_internal.h includes:
47 # include <sys/types.h>
48 # include <stdbool.h>
49 # include <netinet/in.h>
And netinet/in.h includes:
46 #include <sys/types.h>
47 #include <sys/socket.h>
48 #include <stdint.h>
Which is where the collision error is introduced since up_wpcap.c includes winsock2.h already. There were additional problems introduced to the file by other changes:
- A malformed syslog() call was added
- Some issues with netdriver_setmacaddr()
When the Head to Tail relationship was H < T, then
only the tail to end of buffer was sent.
The fix is: In the txdma completion to do a second
the DMA operation using nbuffer if the nlength is
non zero.
stm32f7:serial UART5 use actual size
UART5 was using the CONFIG_UART5_TXBUFSIZE
not the UART5_TXBUFSIZE_ADJUSTED.
Since the buffer size was adjusted up, this
has no dcache implications.
If the UART5_TXBUFSIZE_ADJUSTED is larger
then CONFIG_UART5_TXBUFSIZE it will present
a larger usable buffer to the system's
serial driver.
## Summary of Changes
Add a host timer that generates periodic signals and sends SIGALRM to
the process that runs the NuttX simulation. This logic is integrated as
part of the existing NuttX oneshot timer. The host timer installs an
irq handler which is expected to run every CONFIG_USEC_PER_TICK .
Signed-off-by: Sebastian Ene <nuttx@fitbit.com>
