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f00c6d3047
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20952 Commits

Author SHA1 Message Date
Petro Karashchenko
f00c6d3047 arch/arm: fix declaration of extern types 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2023-07-31 18:56:40 -07:00
yangyalei
fde8affe71 singal: add stack_t define 
stack_t used by sigaltstack, make it compile sucess in sim.

Signed-off-by: yangyalei <yangyalei@xiaomi.com>

ltp: fix compile errors

Signed-off-by: yangyalei <yangyalei@xiaomi.com>
 2023-07-31 07:50:10 -07:00
Ville Juven
61460efe3c riscv/qemu-rv: Add FPU support back to qemu-rv 
The FPU restore issue does not show itself any longer, so FPU support
can be re-enabled.
 2023-07-31 07:48:53 -07:00
Ville Juven
d0fbf9883d riscv/lazyfpu: Add option to disable lazy FPU 
Adds option to use the old implementation where FPU is stored into
the process stack.
 2023-07-31 07:48:53 -07:00
Ville Juven
4a468b8d3b riscv/saveusercontext: Fix FPU state save 2023-07-31 07:48:53 -07:00
Ville Juven
0ea9debfce riscv/riscv_fpu: Clear the full FPU status/control register on boot 
Instead of clearing the fields individually, just wipe the whole register.
This can be done because flags and rm are just parts of the fcsr.

31             8        5           0
+--------------+--------+-----------+
|              |        |           |
|   RESERVED   |  FRM   |  FSTATUS  |
|              |        |           |
+--------------+--------+-----------+
                FCSR
 2023-07-31 07:48:53 -07:00
Ville Juven
b409d72e9d riscv/fpu: Restore correct lazy-FPU functionality 
- Save the FPU registers into the tcb so they don't get lost if the stack
  frame for xcp.regs moves (as it does)
- Handle interger and FPU register save/load separately
- Integer registers are saved/loaded always, like before
- FPU registers are only saved during a context switch:
  - Save ONLY if FPU is dirty
  - Restore always if FPU has been used (not in FSTATE_OFF, FSTATE_INIT)
- Remove all lazy-FPU related logic from the macros, it is not needed
 2023-07-31 07:48:53 -07:00
Ville Juven
3b5c0c885f riscv/swint: Give the full tcb to the context switch routine 
Why? The tcb can contain info that is needed by the context switch
routine. One example is lazy-FPU handling; the integer registers can
be stored into the stack, because they are always stored & restored.

Lazy-FPU however needs a non-volatile location to store the FPU registers
as the save feature will skip saving a clean FPU, but the restore must
always restore the FPU registers if the thread uses FPU.
 2023-07-31 07:48:53 -07:00
Bowen Wang
28cb5e7984 arm64: add kasan support for arm64 
Add kasan compiler option in arm64 Toolchain.defs

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
 2023-07-31 05:45:46 -07:00
zhangyuan21
f9cab5b9dc arch/arm64: add ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE config 
Enable dcache and icache when ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE
disabled at __start.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
 2023-07-31 05:33:23 -07:00
Bowen Wang
d24622888f arm64_backtrace: use running_task if arch_get_current_tcb return NULL 
In the init phase of the OS, arch_get_current_tcb return NULL. Enable
the memory backatrace default will crash in backtrace function.

Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
 2023-07-31 04:52:49 -07:00
zhangyuan21
c6f32f4363 arm-m: Check the dcache status before enabling dcache 
If the cache is already enabled before NuttX starts up,
enabling the cache in NuttX will cause the cache to be
re-invalidated, then resulting in data that is already
in the cache being flushed out.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
 2023-07-31 08:49:21 +02:00
Xiang Xiao
fc5e85da1b drivers: Format pointer through "%p" for kthread_create 
to remove the unnecessary cast and unify the usage

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-07-30 23:40:59 +03:00
yuexinyi
56be0ab050 drivers/video: add capture arg to support multi instance 
Signed-off-by: yuexinyi <yuexinyi@xiaomi.com>
 2023-07-29 07:42:29 -07:00
hujun5
e3f481d3b1 arm/trustzone: time interrupt setting failed 
we should use a secure clock when the CPU is in secure mode

Signed-off-by: hujun5 <hujun5@xiaomi.com>
 2023-07-29 06:58:24 -07:00
dongjiuzhu1
d89e0996f5 sim/usbdev: Add string table as it is needed when USBTRACE is turned on 
nuttx/drivers/usbdev/usbdev_trprintf.c:418: undefined reference to `g_usb_trace_strings_intdecode'
/usr/bin/ld: nuttx/drivers/usbdev/usbdev_trprintf.c:496: undefined reference to `g_usb_trace_strings_deverror'

Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
 2023-07-28 20:58:23 -07:00
dongjiuzhu1
ddc2c62aa8 sim/rawgadget: don't push fifo if ioctl failed because it will cause busy read 
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
 2023-07-28 20:58:23 -07:00
dongjiuzhu1
14446677d3 arch/arm64: default select ARCH_HAVE_SETJMP 
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
 2023-07-28 20:57:26 -07:00
dongjiuzhu1
7d281f46de sim/hostfs: fix issue about access file with size more than 2GB 
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
 2023-07-28 07:42:12 -07:00
Tiago Medicci Serrano
8673e659b4 espressif: quiet git commands and improve build logging 
Add `--quiet` to git commands to avoid unnecessary logging during
the operation and add summarized logs to show progress.
 2023-07-27 19:43:48 -07:00
Tiago Medicci Serrano
e38b4b2103 espressif: fix linker to include the reserved area of RTC memory 
Basically, it reserves an area of the RTC memory to preserve the
RTC timer.

Please refer to:
fa76c82a5b

This commit also removes the rtc.dummy section because C3, C6 and
H2 don't need to skip it once the region is accessed by the same
address space using the instruction and data bus.
 2023-07-27 19:43:48 -07:00
Tiago Medicci Serrano
8e343405a2 espressif: update esp-hal-3rdparty 
The esp-hal-3rdparty release include general bugfixes.
 2023-07-27 19:43:48 -07:00
hujun5
68187b68af arch: move [enter|leave]_critical_section 
move [enter|leave]_critical_section to the same place for easy to understand
and call matching

Signed-off-by: hujun5 <hujun5@xiaomi.com>
 2023-07-27 11:34:09 +02:00
SPRESENSE
b515f9a360 arch: cxd56xx: Fix compile error 
Add inttypes.h to fix a compile error in cxd56_emmc.c.
 2023-07-26 22:14:31 -07:00
Ville Juven
6bafdd45fd riscv/mpfs: Set hart2 default entrypoint to -1 like the others 
No reason to have a different entrypoint
 2023-07-26 19:58:05 -03:00
anjiahao
2645e59901 sim/tcbinfo:add ebp to tcbinfo 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2023-07-26 06:57:25 -07:00
raiden00pl
ef252fc0fc arch/nrf91/modem: fix returned source address 2023-07-26 04:51:05 -07:00
guoshichao
3524f4b9ce libs/libc/fork: add lib_fork implementation 
1. add lib_fork api in libs/libc, we need a fork() api to implement the
fork relative method, such as pthread_atfork
2. rename the assembly fork entry function name to up_fork(), and rename
the up_fork() to arch specific name, such as
sim_fork()/arm_fork()/mips_fork() etc.

Signed-off-by: guoshichao <guoshichao@xiaomi.com>
 2023-07-26 10:41:52 +02:00
Xiang Xiao
46b25b3849 arch: Compute the array size by nitems 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-07-26 09:33:38 +02:00
Xiang Xiao
7ca4c916eb arch/sparc: Add g_tcb_info 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-07-26 09:33:38 +02:00
Xiang Xiao
94f273130e arch/x86_64: Add g_tcb_info 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-07-26 09:33:38 +02:00
Xiang Xiao
8d46cfd8e5 arch/x86: Add g_tcb_info 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-07-26 09:33:38 +02:00
Xiang Xiao
f3269a6caa sched: Rename DEBUG_TCBINFO to ARCH_HAVE_TCBINFO 
and select if the arch support to define g_tcbinfo variable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2023-07-26 09:33:38 +02:00
anjiahao
d5347d8915 arm64:fix ostest failed to run 
The reason for the failure is incorrect sp,
resulting in the failure to restore the register

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2023-07-25 16:37:49 -03:00
Tiago Medicci Serrano
dacb4e87b6 espressif: get esp-hal-3rdparty sources based on its version 
Clone the esp-hal-3rdparty repository and, then, checkout to a
specific version (usually indicated by the commit SHA) instead of
using a branch as the HEAD.
 2023-07-25 09:44:59 -07:00
raiden00pl
60200b6c9b arch/nrf91: make all interrupts non-secure only if CONFIG_NRF91_SPU_NONSECURE=y 
this fixes configurations that works only in secure environment (for testing and dev purposes)
 2023-07-25 08:49:24 -07:00
raiden00pl
e48d730273 cmake: enable more cmake builds 2023-07-25 06:18:22 -07:00
chao an
49dec5b48c cmake/build: fix build break on cmake 
Signed-off-by: chao an <anchao@xiaomi.com>
 2023-07-25 15:00:10 +02:00
raiden00pl
dffb472ad9 cmake: port stm32f0l0g0 2023-07-24 10:13:26 -07:00
zhangyuan21
9792211b96 sched/tcbinfo: add stack info to tcbinfo 
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
 2023-07-24 09:47:12 -07:00
anjiahao
8abf803a1d arm64:Need to store native sp pointer to tcb 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2023-07-23 21:59:35 -07:00
anjiahao
ceb6bb6650 arm64:support arm64 for tcb info 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2023-07-23 21:59:35 -07:00
anjiahao
eadfdab9a7 sim:add sim32 & sim64 tcbinfo 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2023-07-23 21:59:35 -07:00
anjiahao
9f644579b3 fix sim register & tcb info typo 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2023-07-23 21:59:35 -07:00
kcheshmedzhiev
ea87d008a0 Initial support for NUCLEO-U5A5ZJ-Q board 
Fix for ci error

Typo changes

Fixed typo in boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c

Typo changes

Typo fixes

Typo fixes

Typo changes

Typo changes

Typo changes
 2023-07-23 18:42:05 -07:00
Victor Benso
0c5145b7d1 New implementation of the ESP32's RMT driver. 2023-07-23 16:17:57 -03:00
raiden00pl
eb965d5fec arch/nrf91: add support for modem sockets 2023-07-23 19:56:38 +08:00
raiden00pl
6bd5452588 arch/nrf91: fixes for modem OS integration 2023-07-23 19:56:38 +08:00
raiden00pl
aa5ac49a21 arch/nrf91: convert modem AT interface to serial device 2023-07-23 19:56:38 +08:00
raiden00pl
b3c5e05add arch/nrf91: fix modem initialization 2023-07-23 19:56:38 +08:00