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Author SHA1 Message Date
SPRESENSE
22d2ef0bf4 boards: cxd56xx: Make board_late_initialize a weak function 
Add a weak_function to the board_late_initialize function so that
it can be replaced by another file, such as a user application.
 2022-04-12 07:55:00 +09:00
SPRESENSE
c2e45444ff boards: cxd56xx: Fix an issue i2c tool not working 
It caused i2c tool not to work due to i2c uninitializing processing.
Since this process is not necessary in the normal case, we will
move it to the error case.
 2022-04-12 07:55:00 +09:00
SPRESENSE
39f7c4aea0 arch: cxd56xx: Fix critical section in scu driver 
Add critical section to scu one-shot sequencer.
 2022-04-12 07:55:00 +09:00
SPRESENSE
e725829547 cxd56xx/cxd56_emmc.c: Fix compile warning 
Add necessary include header named debug.h for using ferr and
finfo.
 2022-04-12 07:55:00 +09:00
SPRESENSE
5be940080b arch: cxd56xx: update loader and gnssfw version 
Update loader and gnssfw to version 2.2.20585
 2022-04-12 07:55:00 +09:00
chao.an
a594a5d7a8 sched/init: drivers_initialize() should be late than up_initialize() 
up_initialize
|
 ->up_serialinit
   |
    ->uart_register  /* ("/dev/console", &CONSOLE_DEV); */

drivers_initialize
|
 ->syslog_console_init
   |
    ->register_driver /* ("/dev/console", &g_consoleops, 0666, NULL); */

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-12 07:51:34 +09:00
Ville Juven
2670f143b5 RISC-V: Add setintstack for k210 and qemu 
This fixes CI issue, and I think the old implementation with SMP
shared 1 IRQ stack for multiple CPUs.
 2022-04-12 01:59:35 +08:00
Ville Juven
b0a71ce3e7 RISC-V: Remove riscv_cpuindex.c from platforms that don't need it 
riscv_mhartid is no longer called by exception_common, so can remove
this file from platforms that don't need it.

Also fixes make warning:
Makefile:123: target 'riscv_cpuindex.o' given more than once in the same rule
 2022-04-12 01:59:35 +08:00
Ville Juven
d5ea259828 RISC-V: Combine 3 variables that depend on CPU amount into one 
IRQ_NSTACKS, ARCH_CPU_COUNT, CONFIG_SMP_NCPUS all relate to each
other. However, a bit of clean up can be done and everything can
be merged into SMP_NCPUS.

The MPFS bootloader case works also as it requires only 1 IRQ stack
for the hart that executes as bootloader.
 2022-04-12 01:59:35 +08:00
anjiahao
bb6279fe60 libc/lib_localtime:fix deadcode 
isdst always is false

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-12 01:51:29 +08:00
Petro Karashchenko
ea5ffac7d1 drivers/syslog: update description if Kconfig 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-04-11 23:36:39 +08:00
SPRESENSE
46a92aeebb graphics/nxterm: Avoid accessing freed memory 
Fix accessing freed priv data.
 2022-04-11 20:50:09 +08:00
songlinzhang
8dd5d0d510 netdb/lib_dnsaddserver.c: Do not insert the duplicate DNS address 
Signed-off-by: songlinzhang <songlinzhang@xiaomi.com>
 2022-04-11 20:31:15 +08:00
YAMAMOTO Takashi
c9f3b3a7f1 littelfs: deal with block devices w/o ioctl 
Note: Some block devices has ioctl == NULL. eg. drivers/loop
 2022-04-11 13:38:26 +03:00
SPRESENSE
9cd53d714e drivers/sensors/sgp30: Fix redundant parameter check 
Fix redundant conditions.
 2022-04-11 13:29:35 +03:00
SPRESENSE
3787a362bf drivers/sensors/scd30: Fix invalid parameter check 
Fix invalid parameter check and redundant conditions.
 2022-04-11 13:29:35 +03:00
SPRESENSE
bf332cf888 drivers/sensors: Add new driver for scd41 sensor module 
Add Sensirion's SCD41 CO2, temperature and humidity sensor driver.
 2022-04-11 13:29:35 +03:00
chao.an
609e949ab0 sched/note: include-able from C++ files 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-11 16:30:27 +08:00
Xiang Xiao
a90bdda1ae arch/riscv: Add mtimer driver 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-11 10:59:18 +03:00
wangbowen6
d4978bfba4 mm_initialize: malloc() return aligend pointer. 
malloc() should return aligned (with MM_MIN_CHUNK) pointer, but
pr #5906 destroy that, this pr find a better method to solve
these questions.

Signed-off-by: YAMAMOTO Takashi <yamamoto@midokura.com>
and
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-04-11 12:46:17 +08:00
wangbowen6
1a4ccd2d70 Revert "mm_heap: heapsize align with MM_MIN_CHUNK." 
This reverts commit 69e69740b5.
 2022-04-11 12:46:17 +08:00
okayserh
218cbb470a Fixed source code format errors. 2022-04-10 19:12:10 -03:00
okayserh
56f0d72465 Minor fix, function name was wm8994_setvolume instead of 
wm8904_setvolume.
 2022-04-10 19:12:10 -03:00
okayserh
eb3e8175de Fixes some issues with the implementation of the balance 
functionality. In function "wm8904_hw_reset" the priv->balance
is initialized with b16HALF, indicating a range from
0 to b16ONE. In function "wm8904_setvolume" the assumed
range for priv->balance is between 0 and 1000. The changes
now make this consistent for 0 to b16ONE-1. Furthermore,
in wm8904_configure the change of balance was not implemented.
 2022-04-10 19:12:10 -03:00
Xiang Xiao
1a6ee1b908 audio: Don't register audio device if name isn't given in audio_comp_initialize 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-10 15:41:14 -03:00
zhangyuebin
f3d20abe07 audio: Return audio_lowerhalf_s pointer instead error code in audio_comp_initialize 2022-04-10 15:41:14 -03:00
nietingting
dd70d29d4e tools/mkdeps: Extend MAX_SHQUOTE to 3072 
Signed-off-by: nietingting <nietingting@xiaomi.com>
 2022-04-10 09:55:14 +03:00
Ville Juven
a132fa38f6 riscv/bl602/chip.h: Add assembly guards for standard includes. 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
779fc6461f riscv/esp32c3: Use the common exception handler. 
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
e8134a8b57 riscv/riscv_exception_common.S: Allow chips to define the exception 
section.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
Abdelatif Guettouche
875dd46207 riscv/riscv_exception_commin.S: Don't call riscv_hartid in single core 
mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-04-10 08:27:10 +08:00
liuhaitao
c4e2d88e6b Make top Make.defs symlink to board Make.defs instead 
Symlink to board Make.defs for top Make.defs, so top Make.defs
syncs in realtime.

Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
 2022-04-10 01:28:27 +02:00
Xiang Xiao
0f82eccc4f .github/workflows/check.yml: Enable Change-ID check explicitly 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-09 22:06:54 +02:00
liuhaitao
c998a2c9bf checkpatch.sh: add -m option to enable/disable Change-Id check 
Defaultly disable Change-Id check in commit message.

Signed-off-by: liuhaitao <liuhaitao@xiaomi.com>
 2022-04-09 22:06:54 +02:00
Huang Qi
9284770f75 arch/risc-v: Move epc adjustment to riscv_doirq 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Huang Qi
833211680a arch/risc-v: Attach exception handler in common place 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Huang Qi
36bc8d2131 arch/risc-v: Align prototype of riscv_exception with xcpt_t 
Thus we can attach it to irq handler without any cast.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-10 00:52:04 +08:00
Xiang Xiao
c235c0fa43 boards/lx_cpu: Enable up_perf API 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-08 21:02:13 -03:00
Xiang Xiao
1f7b49d700 boards/nucleo-h743zi2: Enable up_perf API 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-08 21:02:13 -03:00
Xiang Xiao
51ffa3edb0 sched/irq: Fix array overrun in coverity check 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-08 21:02:13 -03:00
Xiang Xiao
aed5dadc3d sched/irq: Remove CONFIG_SCHED_IRQMONITOR when define CALL_VECTOR 
since up_perf_ API doesn't couple with CONFIG_SCHED_IRQMONITOR

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-08 21:02:13 -03:00
Xiang Xiao
bf3da321c9 sched/wqueue: Simplify CALL_WORKER dispatch condition 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-08 21:02:13 -03:00
Xiang Xiao
074beff551 tools/checkrelease.sh: Don't check DISCLAIMER-WIP anymore 
since all license is clean up now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-04-08 21:00:56 -03:00
Huang Qi
c6942b68d5 arch/risc-v: Add handler for misaligned load/store 
Some risc-v based chips don't support unaligned data access,
it will trigger a exception and then lead to crash.

In this patch, we handle the misaligned access by software to make
system run continue.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-08 23:27:07 +08:00
yinshengkai
4b6743591a fs/vfs: fix st_mode mask check 
The full mask for st_mode is 0177777
Now modify any file permissions in hostfs and all will fail
 2022-04-08 15:06:41 +03:00
chao.an
8d66dbc068 arm/armv[7|8]-m: skip the fpu save/restore if stack frame is integer-only 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-08 14:28:41 +09:00
chao.an
8cb008c3c7 sched/note: correct flatten format 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-08 02:41:25 +08:00
chao.an
ef89f3f15a sched/note: add dummy definition if CONFIG_SCHED_INSTRUMENTATION disabled 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-04-08 02:41:25 +08:00
anjiahao
47304e7254 sched/pthread:need check pthread is DETACHED 
pthread_join need check thread is DETACHED,
Whether to wait according to the result.And,
if a thread is DETACHED,it will not set a new
attr.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
 2022-04-08 01:41:06 +08:00
Huang Qi
b6cf1ac662 arch/riscv: Minor style change and text correction 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-04-08 01:07:06 +08:00