Situation:
Assume we have 2 cpus, and busy run task0.
CPU0 CPU1
task0 -> task1 task2 -> task0
1. remove task0 form runninglist
2. take task1 as new tcb
3. add task0 to blocklist
4. clear spinlock
4.1 remove task2 form runninglist
4.2 take task0 as new tcb
4.3 add task2 to blocklist
4.4 use svc ISR swith to task0
4.5 crash
5. use svc ISR swith to task1
Fix:
Move clear spinlock to the end of svc ISR
Signed-off-by: ligd <liguiding1@xiaomi.com>
it inappropriate to apply volatile to the task list:
1.The code access task list is already protected by critical section
2.The queue is complex struct, it isn't enough to protect by volatile
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
because not all compiler support the weak attribute, and
many features are either always used or guarded by config.
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
1.Forward nxsched_process_cpuload to nxsched_process_cpuload_ticks directly
2.Define the dummy nxsched_process_cpuload_ticks when CPULOAD isn't enabled
3.Remove the weak attribute from nxsched_process_cpuload_ticks
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
and remove CONFIG_LIBC_LONG_LONG option to simplify the usage.
note: the size will increase 668
before change:
text data bss dec hex filename
168440 348 4480 173268 2a4d4 nuttx
after change:
text data bss dec hex filename
169108 348 4480 173936 2a770 nuttx
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
1. fix typo spilock -> spinlock
2. fix build break
sched/sched_note.c: In function ‘note_spincommon’:
sched/sched_note.c:435:3: error: aggregate value used where an integer was expected
435 | note.nsp_value = (uint8_t)*spinlock;
| ^~~~
Signed-off-by: chao.an <anchao@xiaomi.com>
The implementation of this feature is based on android systrace:
https://source.android.com/devices/tech/debug/ftrace
Application developers are more concerned about the performance of
the specified application section,
added two APIs to implement performance measurement:
void sched_note_begin(uintptr_t ip, FAR const char *buf);
void sched_note_end(uintptr_t ip, FAR const char *buf);
or
SCHED_NOTE_BEGIN(); /* defined to sched_note_begin(_THIS_IP_, __FUNCTION__) */
SCHED_NOTE_END(); /* defined to sched_note_end(_THIS_IP_, __FUNCTION__) */
Signed-off-by: chao.an <anchao@xiaomi.com>
Perf timer interface generally uses the hardware cycle counter
provided by the arch chip directly(such as DWT_CYCCNT(cortex-m)),
CYCCNT is a free running counter and counting upwards.
It wraps around to 0 on overflow.
Signed-off-by: chao.an <anchao@xiaomi.com>
The BUG is as follow:
1. Suppose there are two ready tasks t1 and t2 have the same priority, and t1 is the running.
2. A new, higher priority task t0 (such as hpwork) is ready, then switch to t0.
3. After t0 is suspended, then switch to t1 and reset the t1's timeslice.
4. goto 2
The t2 will have no chance to run.
Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>
1. If CONFIG_SCHED_INSTRUMENTATION_SWITCH is enabled, then these additional interfaces are expected:
sched_note_suspend
sched_note_resume
at the same time，If CONFIG_SMP is enabled，then expected：
sched_note_cpu_pause
sched_note_cpu_paused
sched_note_cpu_resume
sched_note_cpu_resumed
2. other board if enable SCHED_INSTRUMENTATION，SCHED_INSTRUMENTATION_SWITCH to defconfig.
If a task registers SIGCHLD, uses waitpid(-1)
in the handler, and the task also calls waitpid,
it will fail to delete the child function
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Fix the regression by commit:
commit 8b67944c75
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date: Thu Oct 14 11:03:07 2021 +0800
sched: Remove pidhash_s and move ticks to tcb_s
simplify the code logic and reduce memory a little bit
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
