We can see them in ifconfig:
ap> ifconfig
wlan0 Link encap:Ethernet HWaddr 42:64:7f:b3:12:03 at UP mtu 1500
inet addr:10.0.1.2 DRaddr:10.0.1.1 Mask:255.255.255.0
inet6 DRaddr: ::
RX: Received Fragment Errors Bytes
00000b9b 00000000 00000000 21daf5
IPv4 IPv6 ARP Dropped
00000a33 00000137 00000031 00000000
TX: Queued Sent Errors Timeouts Bytes
00000ac4 00000ac4 00000000 00000000 1a2103
Total Errors: 00000000
Signed-off-by: meijian <meijian@xiaomi.com>
Since the introduction of the rp2350, the pico-sdk project has been
re-arranged and elf2uf2 has been merged in to a new 'picotool' binary
which is supplied and installed separately.
Make umm & kmm heap alloc more clear, and possible support FLAT build to
enable kernel heap.
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
1. correct the armv8-r fpu flag from vfpv3-d16 to fpv5-sp-d16
2. add neon support
This commit updates the build script to specify the FPU type of
`fpv5-sp-d16` when the processor is configured with a single-precision
FPU, and `neon-fp-armv8` when the processor is configured with a
double-precision + Advanced SIMD-capable FPU.
Note that the `fp-armv8` FPU type is an alias for double-precision FPv5
with 32 double-precision registers (refer to the GCC
`gcc/config/arm/arm-cpus.in` for more details); NEON is always
specified in case of a double-precision configuration because the
Cortex-R52 can only be configured as such.
Reference:
https://developer.arm.com/Processors/Cortex-R52
Instruction set:
Arm and Thumb-2. Supports DSP instructions and a configurable Floating-Point
Unit either with single-precision or double precision and Neon.
Signed-off-by: chao an <anchao@lixiang.com>
Make this_cpu is arch independent and up_cpu_index do that.
In AMP mode, up_cpu_index() may return the index of the physical core.
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
In corner case, the pending ISR will be triggered immediately
after enable the IRQ, this PR will setting CPU affinity first
to avoid routing the unexpected IRQ to other CPUs.
Signed-off-by: chao an <anchao@lixiang.com>
Some USB controllers can receive or send multiple data packets then
generate one interrupt. This mechanism can reduce the number of data
copies. Extend req buf to accommodate this.
Signed-off-by: yangsong8 <yangsong8@xiaomi.com>
In protected build mode, the syscall returns without setting correct value for the CONTROL register, which causes the userspace threads working in privileged mode after syscall.
Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
Currently concerns only arm.
tools/ci/testlist/msys2.dat:
At the moment I only added the board nucleo-l152re:nsh
.github/workflows/build.yml:
Enabled cmake for msys2
since not all Armv7-m platform support double-precision floating
operations, so we add an extra option that help those specific platform
could define the single-precision floating operations.
for example, qemu-mps platform(armv7-m) support double-precision
floating operations, so we do not need to open
CONFIG_ARM_FPU_SINGLE_HARDWARE build options;
but for fc7300 platform(armv7-m) only support single-precision floating
operations, so if we pass "-fhard" build option to "ghs" compiler, then
the following instruction will be generated:
vcvt.f64.s32 d9, s18
which will fail to execute on fc7300 platform.
with "-fsingle" build option, the "ghs" compiler will generate hardware
instruction for single-precision floating operation, and generate
software instruction for double-precision floating operation.
Signed-off-by: guoshichao <guoshichao@xiaomi.com>
To support greenhill compilation, LDFLAGS removes the code that adds -T through addprefix to ARCHSCRIPT(greenhill requires a space between -T and ldscript files, but addprefix didn't do it). However,if we modified like this, when ARCHSCRIPT has more than one ldscript, the -T is only added to the first ldscript, but not to the following ldscripts, which results in a warning when linking.
To solve this problem, we can just add a space after $(SCRIPT_OPT) when using addprefix, instead of deleting addprefix.
Signed-off-by: pangzhen1 <pangzhen1@xiaomi.com>
Only in the non-critical region， nuttx can the respond to the irq and not hold the lock
When returning from the irq, there is no need to check whether the lock needs to be released
we also need keep restore_critical_section in svc call
test:
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
-machine virt,virtualization=on,gic-version=3 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hujun5@xiaomi.com>
armv7-m/arm_mpu.c: In function 'mpu_dump_region':
armv7-m/arm_mpu.c:621:13: warning: format '%X' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int' [-Wformat=]
621 | _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv7-m/arm_mpu.c:621:13: warning: format '%X' expects argument of type 'unsigned int', but argument 6 has type 'long unsigned int' [-Wformat=]
621 | _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv7-m/arm_mpu.c:621:13: warning: format '%X' expects argument of type 'unsigned int', but argument 7 has type 'long unsigned int' [-Wformat=]
621 | _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
armv7-m/arm_mpu.c:621:13: warning: format '%u' expects argument of type 'unsigned int', but argument 8 has type 'long unsigned int' [-Wformat=]
621 | _info("MPU-%d, alignedbase=0%08X l2size=%"PRIu32" SRD=%X"
Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
Modified the input parameters of mpu_initialize to require the caller to provide the number of entries in the table
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
Summary:
1.Modify the conditions for entering different include header files
2.Added pre-definition for _Atomic _Bool when it is missing
3.Added nuttx for stdatomic implementation. When toolchain does not support atomic, use lib/stdatomic to implement it
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
In a multicore task scenario, there may be a situation where the task runs on different cores at different time slices (when the task is not bound to a particular core).
When the task calls cache clean/flush(range > cache size), depending on the optimization, clean_all, flush_all are called. however, at this point, there may be dirty data or incomplete data profiles in the cache on the kernel that is running the task, which may result in dirty data being flushed into memory or make the application think that the flushed data should be successfully flushed into memory, leading to unknown consequences.
Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
