Commit Graph

326 Commits

Author SHA1 Message Date
Jouni Ukkonen
8382916d26 Map iMX93 OCRAM memory to mmu
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-05-31 10:22:27 +08:00
Jouni Ukkonen
e8de8cf60a Add S3MUA base address for Security Enclave
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
2024-05-31 10:22:27 +08:00
xuxin19
275ec7102c cmake:bugfix CMake compilation options settings should not use strings
when repeatedly enabling and disabling string-controlled configurations,
the generated toolchain configuration may be incorrect.

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2024-05-30 10:02:10 -03:00
Eero Nurkkala
2f753a48c7 arm64: s/ARCH_BOOT_EL3/ARCH_ARM64_EXCEPTION_LEVEL/g
Search and replace ARCH_BOOT_EL3 with more generic
ARCH_ARM64_EXCEPTION_LEVEL that holds the EL level
in an integer variable.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
Eero Nurkkala
1d3ce6b527 arm64/imx9: provide EL3 bootloader support for iMX9
This provides a capable bootloader that may be run from OCRAM.
The OCRAM contains regions that are always zero, so the linker
file avoids those with best effort.

iMX9 infrastructure expects:
  - 0x20480000 (Start of OCRAM, AHAB)
  - 0x2049a000 (NuttX or SPL)
  - 0x204e0000 (ARM Trustzone, not used)

When started from SD-card, the offsets are:
  - 0x1f000 with AHAB
  - 0xa000  without AHAB

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
Eero Nurkkala
1c308296a1 arm64: provide EL3 interrupt support via FIQs
Value 1021, when read from ICC_IAR0_EL1 means:

"The GIC returns this value in response to a read of ICC_IAR0_EL1 or ICC_HPPIR0_EL1 at EL3,
to indicate that the interrupt being acknowledged is one which is expected to be handled at
Non-secure EL1 or EL2. This INTID is only returned when the PE is executing at EL3 using
AArch64 state, or when the PE is executing in AArch32 state in Monitor mode."

When this happens:
  - FIQ is fired on group0
  - IRQ is pending at group1

So simply check and handle the interrupt. In short, this provides interrupt support for
EL3.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
Eero Nurkkala
505f57dd00 arm64: introduce MMU support for EL3
Currently MMU supports only EL1.  Introduce EL3 support as well.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
Eero Nurkkala
0f9a262311 arm64: provide EL3 support
This provides means to run NuttX completely in EL3.  This may
be useful with NuttX based bootloaders that are executed from
OCRAM.  Instead of SPL/U-boot combo, NuttX may replace SPL
completely.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
Eero Nurkkala
ae00569ef9 imx9_clockconfig: fix a thinko
putreg32() arguments were swapped.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2024-05-21 09:02:35 +08:00
yinshengkai
20ebe0e64c Replace all asserts in kernel code with ASSERT
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-05-17 10:18:16 -03:00
hujun5
6c1b900e82 arm64: optimise for arm64_switchcontext
We can save execution time by
       inline arm64_fullcontextrestore and arm64_switchcontext

test:
We can use qemu for testing.

compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-14 16:03:08 -03:00
simbit18
d1789d84e8 fix nxstyle
fix Relative file path does not match actual file.
2024-05-13 22:24:36 +02:00
hujun5
5cee996588 up_putc: int up_putc, enter_critical_section may be called
before kernel has been iniitialized,we use spin_lock_irqsave to replace.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2024-05-09 13:45:02 +08:00
Jani Paalijarvi
5b3ef20629 arm64/imx9: Allocate 64B granules instead of 256B
Optimal size of granule is 64B (the dcache line size).
We can use it now as we don't have max. 32 granules limitation anymore.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-08 08:48:12 +08:00
Jani Paalijarvi
0d3a1bc617 arm64/imx9: Fix fat_dma_ macro issue.
Defining fat_dma_alloc(s) as imx9_dma_alloc(s) causes compiler errors.

Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-08 08:48:12 +08:00
Jani Paalijarvi
c11ffaa78f arm64/imx9: Add DMA preflight support for uSDHC
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-08 08:48:12 +08:00
Jani Paalijarvi
602bd685ec arm64/imx9: Add uSDHC driver
Signed-off-by: Jani Paalijarvi <jani.paalijarvi@unikie.com>
2024-05-08 08:48:12 +08:00
Jukka Laitinen
cc9c3ed80b arch/arm64/src/imx9: Add Ethernet driver
This adds a driver for i.MX93 ENET1 MAC block

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-05-02 16:30:41 -03:00
Ville Juven
3b5b755d1e arch/imx9_lpspi: Use DMA safe buffers to do the DMA transfers
Using user allocated buffers for DMA transfers is not safe for two reasons:
- User space memory is virtual memory, DMA needs physical memory
- User memory buffer alignment cannot be guaranteed -> cache line ops
  are not safe
2024-04-30 19:46:58 +08:00
Ville Juven
3079caf2ce arm64/imx9: Add DMA memory allocator
Add a simple allocator for DMA safe memory. It will provide contiguous
blocks of memory with D-Cache line size alignment.

NOTE: The optimal granule size is the D-Cache line size (64), but due
to restrictions in the granule allocator this would result in a maximum
block size of 2K only, thus use 256B granules instead givin 8K max block
size.

Once the granule allocator is fixed this limitation can be removed.
2024-04-30 19:46:58 +08:00
Philippe Leduc
3dc6b4c9bd Add basic support for locales in order to C++ streams to build and work for simple cases (POSIX / C locale).
Fix build with C++ GCC toolchain
2024-04-29 17:34:10 +08:00
Ville Juven
0d9a3d94eb imx9_clockconfig: Add way to set PLL frequencies
This patch adds a way to configure PLL frequencies. The configuration is
given by board logic.

These values should only be modified by the bootloader, but we don't have
that yet so the flag is never activated.
2024-04-25 19:24:16 -03:00
Ville Juven
e3f4749a3c imx9_clockconfig: Add way to query / calculate PLL frequencies
The frequency LUT idea is not necessary as the PLL output can be calculated
by the CPU. It is better to do this as the clocks are set by the SPL (2nd
stage program loader) which means the NuttX payload would not have access
to such a LUT anyhow.

The mask PLL_DIV_RDIV_MASK is also fixed, as that was simply wrong.

Also add call to imx9_clockconfig (although it does not do anything yet).
2024-04-25 19:24:16 -03:00
Ville Juven
89752e9993 arm64/imx9: Add eDMA driver
This driver supports both eDMA3 and eDMA4 (also referred to as DMA0 / DMA1
in some contexts..)

The IP blocks are almost identical, with sufficiently minor differences
to use them via a unified driver. The price is a great amount of code
obfuscation in the hardware description layer.
2024-04-24 11:52:53 +08:00
Yanfeng Liu
5c3fc2796b tools/export: fix names for app linker script and program entry.
This fixes names of program entry and linker script files so that to
support building kernel mode apps using CMake and export package.

flat and protected mode should be the same as before.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-04-24 11:40:16 +08:00
Ville Juven
1b7a95c756 arch/imx9: Add PSCI (system reset) support
ARMv8.2-A has PSCI -> it also has support for system reset
2024-04-23 21:30:56 +08:00
Jukka Laitinen
33d0276f3e arch/arm64/src/imx9/imx9_lpuart.c: Change ARMV8M_DCACHE_LINESIZE -> ARMV8A_DCACHE_LINESIZE
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-20 18:43:41 +08:00
Jukka Laitinen
155c776ba8 arch/arm64/src/imx9/imx9_usbdev.c: Fix the descriptor alignments and cache management
Align all the dtd and dqh on cache line boundaries and clean up the cache management

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-20 18:43:41 +08:00
Ville Juven
d73aab9f71 arm64/imx9: Add LPSPI driver
Add driver for LPSPI

Co-authored-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-18 10:58:02 -03:00
Ville Juven
169dd50a08 imx9_gpioirq: Fix testing of ICR field from pinset
icr is tested below with macros like GPIO_INT_LOWLEVEL et al. Those macros
are shifted left by GPIO_INTCFG_SHIFT, so the temporary icr variable
should not be shifted right.
2024-04-18 00:40:07 +08:00
Ville Juven
09a6c400f6 imx9_boot.c: Add initialization of pin interrupts
Initialize the pin interrupt support during boot
2024-04-18 00:40:07 +08:00
Jukka Laitinen
58f0ee6364 arch/arm64/src/imx9: Add a more capable uart driver
Add an uart driver supporting LPUART1-8, dma, flow control, tc etc.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-17 00:10:10 +08:00
Ville Juven
4a82838be7 imx9_iomux.h: Fix issues with the header file
- Add missing include guard
- Add missing C++ guard
- Fix the initialization ordering in IOMUX_PADCFG macro. Why ? Becaused of:

imx9_iomuxc.h:54:3: error: designator order for field 'iomux_padcfg_s::dsyreg' does not match declaration order in 'iomux_padcfg_s'
   54 |   }
      |
2024-04-16 10:56:33 -03:00
Ville Juven
f8c5b91522 arm64/imx9: Add LPI2C driver 2024-04-16 19:14:43 +08:00
Ville Juven
8e32a3ce24 imx93_gpioirq: Fix the GPIO interrupt source names
The original assumption was that the interrupt numbers are divided
so that 16 pins from 1 port are handled by a single interrupt source.

So source 0 would handle pins 0-15 and source 1 would handle pins 16-31.
This assumption is wrong, each pin has two sources, thus there are two
interrupt lines for each pin.

The driver uses source 0, and leaves source 1 disabled.
2024-04-16 19:11:31 +08:00
simbit18
b0504f1e5e fix nxstyle
fix Relative file path does not match actual file.
2024-04-15 15:33:17 -03:00
Ville Juven
2e638f6f19 arch/arm64: Add atomic modifyregXX
These are needed by drivers
2024-04-15 11:53:13 -03:00
Jukka Laitinen
729e9fc8e3 arch/arm64/src/Toolchain.defs: Add -mcpu=cortex-a55 if CONFIG_ARCH_CORTEX_A55 is defined
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-09 19:39:33 -03:00
Xiang Xiao
4ea2aeff6b arch: Remove xxx_intstack_top and xxx_intstack_alloc
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2024-04-09 16:59:00 -03:00
ligd
4e725ecd44 arch: color the intstack for all the CPUs
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
ligd
3844efb5b8 stack: update up_get_intstackbase API to support cpu id
For crash dump all the CPU intstack

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-04-09 16:59:00 -03:00
Jukka Laitinen
5e5640992d arch/arm64/src/imx9/imx9_flexio_pwm.c: Fix wrong input scale and pulse width
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-08 03:02:42 +08:00
W-M-R
0ede3fc377 kasan: Implementing global variable out of bounds detection
Extracting global variable information using scripts:
kasan_global.py:
1. Extract the global variable information provided by the -- param asan globals=1 option
2. Generate shadow regions for global variable out of bounds detection
Makefile:
1. Implement multiple links, embed the shadow area into the program, and call it by the Kasan module

Signed-off-by: W-M-R <mike_0528@163.com>
2024-04-07 23:31:13 +08:00
Jukka Laitinen
0f596ec496 arch/arm64/src/imx9: Add TPM based PWM driver for IMX9
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-05 10:13:32 -03:00
Jukka Laitinen
62a64b06bc arch/arm64/src/imx9: Add imx9 usb device driver
This is a modified version from imxrt driver, which has the same controller.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 15:47:32 -03:00
Jukka Laitinen
d1d5a4abfe arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h: Clean up some base address macros
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 15:47:32 -03:00
Jukka Laitinen
4d3b753a1a arch/arm64/include/imx9/imx93_irq.h: Define IRQ_USBx interrupt numbers
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 15:47:32 -03:00
Jukka Laitinen
47f37e84ba arch/arm64/src/imx9: Flex-IO based PWM driver for imx9
This is a high resolution PWM driver, utilizing one 16-bit Flex-IO timer for
generating PWM period and the rest of the timers to generate PWM duty cycles.

This means that the period has to be the same for every PWM generated from one
FLEXIO block, but this way we can get 16-bit resolution for the PWM signals.

For a typical IMX9 HW there are 8 timers for each Flex-IO block, which means
that by using this driver one can get 7 PWM outputs from one block.

This driver can be later extended to have configuration options to use all
8 channels per flex-io by either using 8+8 -bit timer (less resolution) or by
using an external trigger from an LPIT.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-04-04 23:17:59 +08:00
Ville Juven
3294598541 arm64/imx9: Add GPIO, IOMUX and external interrupt support
This adds memory mapped registers and drivers for digital I/O.
2024-04-04 12:12:01 +08:00
Ville Juven
f50c439f21 imx9_clockconfig.c: Add way to query clock frequency
The frequency of a clock source is stored in a LUT. Currently the
LUT contains the PLL frequencies set by the boot ROM code.
2024-04-04 12:12:01 +08:00
Ville Juven
6a6798ed31 arch/arm64: Add the head obj to libarch.a as well
On other platforms libarch.a contains the head object. Some projects
depend on this fact so let's provide the head object in the archive here
as well.
2024-03-25 20:38:53 +08:00
Ville Juven
738bdb95b7 arm64_head.S: Add explicit input section for __start
As __start must be placed at a precise location, a separate, explicit
input section is needed to guarantee this.

Why is this an issue ? NuttX uses --entry=__start which puts __start in
its correct location, but out-of-tree builds won't work, so it more robust
to use an explicit section for the startup code and enforce its placement
in the linker script.
2024-03-23 00:21:54 +08:00
Ville Juven
00986bdd09 arm64/imx9: Add register definitions for LPTMR 2024-03-22 21:37:35 +08:00
Ville Juven
0b8f6af3d6 arm64/imx9: Add register definitions for LPIT 2024-03-22 21:37:35 +08:00
Ville Juven
d2373f4569 arm64/imx9: Add CCM (Clock Controller Module) 2024-03-22 21:37:35 +08:00
Jukka Laitinen
a54f7ffaa8 arch/arm64/src/common: Remove void * arithmetic
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2024-03-22 09:48:31 +08:00
Ville Juven
46bd210ae4 arm64/imx9: Add support for imx9 series SoMs, imx93 implemented
Adds support for NXP i.MX9-series System-on-Module chips.

- Support for i.MX93 is added
- CPU is Cortex A55 / ARMv8.2A
  - The chip also contains a Cortex M33, but no support is provided
- Supported drivers include lpuart only for now
2024-03-20 20:13:14 +08:00
Ville Juven
8d52020fe1 arm64_internal.h: Expose prototype for arm64_lowputc
Useful procedure in many places.
2024-03-20 20:13:14 +08:00
Ville Juven
2bed7c4646 arm64_mmu: Add data synchronization barrier after page tables are written
The page tables must be committed to system memory before we can proceed
enabling the MMU. ISB() is not enough to do this.
2024-03-19 15:46:51 -03:00
zhangyuan21
9c0d2e1a3c armv7-a/gicv2: move IRQ to group1 and group0 as the FIQ
Purpose: make the the os crash when busyloop with interrupt disable

Follow the arm gicv2 spec, if we want to use the IRQ and FIQ
simultaneously when not using the processor Security Externsions.
We should:
1. IRQ to Group 1 and FIQ to Group 0;
2. Set CICC_CTLR.FIQEn to 1;

Then in NuttX:
1. implement the arm_decodefiq and directly crash in it;
2. provide interface to change the IRQ to FIQ, e.g. change the
   watchdog IRQ to FIQ, so the watchdog can trigger even with the
   interrupt disabled (up_irq_save() called);

Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-19 18:24:42 +09:00
Yanfeng Liu
a66c7c3ee1 comments/docs: fix typos in comments
This fix some typos in comments.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-03-06 13:31:50 +08:00
trns1997
54e9e582d5 Use C++ standard lib from toolchain
Signed-off-by: trns1997 <trns1997@gmail.com>
2024-03-06 08:42:44 +08:00
Tiago Medicci Serrano
ae9ef972c0 paging: Rename existing CONFIG_PAGING to CONFIG_LEGACY_PAGING
Current `CONFIG_PAGING` refers to an experimental implementation
to enable embedded MCUs with some limited RAM space to execute
large programs from some non-random access media.

On-demand paging should be implemented for the kernel mode with
address environment implementation enabled.
2024-03-05 09:45:49 +08:00
Marco Casaroli
447cc9698f use apps-or-nuttx-Make.defs for archs
This will allow apps to tweak build configuration of NuttX
2024-03-01 12:59:16 -03:00
ligd
2241969e5a SMP: fix crash when switch to new task which is still running
cpu0 thread0:                        cpu1:
sched_yield()
nxsched_set_priority()
nxsched_running_setpriority()
nxsched_reprioritize_rtr()
nxsched_add_readytorun()
up_cpu_pause()
                                     IRQ enter
                                     arm64_pause_handler()
                                     enter_critical_section() begin
                                     up_cpu_paused() pick thread0
                                     arm64_restorestate() set thread0 tcb->xcp.regs to CURRENT_REGS
up_switch_context()
  thread0 -> thread1
arm64_syscall()
    case SYS_switch_context
     change thread0 tcb->xcp.regs
    restore_critical_section()
                                     enter_critical_section() done
                                     leave_critical_section()
                                     IRQ leave with restore CURRENT_REGS
                                     ERROR !!!

Reason:
As descript above, cpu0 swith task: thread0 -> thread1, and the
syscall() execute slowly, this time cpu1 pick thread0 to run at
up_cpu_paused(). Then cpu0 syscall execute, cpu1 IRQ leave error.

Resolve:
Move arm64_restorestate() after enter_critical_section() done

This is a continued fix with:
https://github.com/apache/nuttx/pull/6833

Signed-off-by: ligd <liguiding1@xiaomi.com>
2024-03-01 21:05:00 +09:00
Yanfeng Liu
3c327efd2f docs/comments: fix some typos
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-01-15 13:22:13 +08:00
chao an
181a31801d arm/armv8r: remove unused serial_pl011.h
Signed-off-by: chao an <anchao@lixiang.com>
2024-01-11 13:39:06 +01:00
fangxinyong
c479ccb8aa sched: move etc romfs mount from nsh to sched/init
Usually the startup script is placed under /etc. The contents of the etc directory
are compiled and linked with Nuttx binary in the form of romfs. After startup,
it will be  mounted by Nsh.

etc is generated by the different boards, that use genromfs and xxd tools to generate
and compile it into the Nuttx, for example: boards/arm/at32/at32f437-mini/tool/mkromfs.sh
The more common method is etc image generated from the content in the corresponding
board/arch/board/board/src/etc directory, and added by Makefile for example:
boards/sim/sim/sim/src/etc.

But in kernel/protected mode, Nuttx kernel and apps are run in different privileged/
non-privileged mode or the isolated binarys, so as that nsh should use syscall to
access Nuttx kernel by exported API. In this scenario, nsh can not mount the etc image
content, because that is generated in board and as a part of Nuttx kernel.

changes:

- move etc romfs mount from nsh to Nuttx, but keep the script to parse and execute.
- move and rename the related CONFIG, move customized nsh_romfsimg.h to etc_romfs.c
  in boards, and no need declaration for romfs_img/romfs_img_len.

This commit changes and updates all configurations in Nuttx arch/board as much as possible,
but if any missing, please refer to the following simple guide:

- rename CONFIG_NSH_ROMFSETC to CONFIG_ETC_ROMFS, and delete CONFIG_NSH_ARCHROMFS in defconfig
- rename the etc romfs mount configs, for example CONFIG_NSH_FATDEVNO to CONFIG_ETC_FATDEVNO
- move customized nsh_romfsimg.h to etc_romfs.c in board/arch/board/board/src and no need
  declaration for romfs_img/romfs_img_len.
- delete default nsh_romfsimg.h, if ROMFSETC is enabled, should generate and compile etc_romfs.c
  in board/arch/board/board/src.

Signed-off-by: fangxinyong <fangxinyong@xiaomi.com>
2024-01-09 21:29:46 -03:00
yinshengkai
9d436b624b tools: support sorting symbol tables by name
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2024-01-04 09:22:57 -08:00
xuxin19
524425573e CMake:init arm64 CMake qemu-armv8a build
this patch contains arm64 Toolchain, arch common, qemu board and arm64 libc modifications.
support using CMake to compile the qemu executable file.

```
 cmake -B build -DBOARD_CONFIG=qemu-armv8a:nsh -GNinja
 cmake --build build -t menuconfig
 cmake --build build
 qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
```
Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2023-12-27 07:27:17 -08:00
yinshengkai
9852428953 fs: procfs add poll support
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
2023-12-26 19:23:13 -08:00
Masayuki Ishikawa
40843b79eb arch: arm64: Fix GICv2 detection
Summary:
- I noticed that qemu-armv8a:netnsh_smp_hv does not detect
  GICv2 on Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
- According to the GIC-400 TRM, it says that the architecture
  version can be obtained from GICC_IIDR (See Table 3-7)
- This commit fixes this issue.

Impact:
- Should be none

Testing:
- Tested with qemu-armv8a:netnsh_smp_hv on
  - Raspi3B+ (ubuntu 22.04 server + qemu-8.1.2)
  - Raspi4B (ubuntu 22.04 server + qemu-8.1.2)
  - M1/MacBook Pro 2021 (macOS 13.6 + qemu-8.1.2)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-12-21 01:21:20 -08:00
Xiang Xiao
ca5a9c711a Remove @ and % tag from all comments
and format the multiple line comments

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-12-11 17:00:10 -03:00
anjiahao
7dfbd14eba libc: add instrument api support
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.

We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.

Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
   becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.

use instrument_register to register entry function and exit function.
They will be called by the instrumented function

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-11 02:06:51 -08:00
anjiahao
90517b9f11 coredump:support arm64 coredump
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-12-08 21:33:03 -03:00
anjiahao
749655d785 tcbinfo:remove total_num form tcbinfo.
total_num is not required
test:

make -f tools/Makefile.host
cp tools/jlink-nuttx /opt/SEGGER/JLink_V786a/libnuttxplugin.so
JLinkGDBServer -if SWD -speed 5000 -device STM32F429ZI -NoGui 1 -rtos libnuttxplugin

can run normally

Signed-off-by: anjiahao <anjiahao@xiaomi.com>
2023-11-21 21:52:24 -08:00
liaoao
6e604741f6 arm64_vector: no need to save x0 to sp
It will cause an incorrect sp value saved in context when saving X0 to sp.

Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-11-21 07:56:19 -08:00
chao an
64cf63475c arch/dumponexit: unify dump on exit to common code
remove arch implement and move to common code

Signed-off-by: chao an <anchao@xiaomi.com>
2023-11-15 08:28:25 -08:00
dongjiuzhu1
8ad88a3fc5 qemu/arm64: implement up_textheap_align and support sotest
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-10-30 18:20:22 +08:00
dongjiuzhu1
da95b35175 arch/arm64: Add declaration for arm64_mmu_set_memregion
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-10-30 18:20:22 +08:00
dongjiuzhu1
489bd15271 arch/arm64: support relocate for aarch64
Signed-off-by: dongjiuzhu1 <dongjiuzhu1@xiaomi.com>
2023-10-30 18:20:22 +08:00
SPRESENSE
f3fabc5d32 Revert "make/archive: Use the full path name when matching or storing names in the archive"
This reverts commit 563125fde3.
2023-10-27 22:26:18 +08:00
simbit18
37729540c0 Fix Kconfig style
Remove spaces from Kconfig
Add comments
2023-10-26 01:53:58 +08:00
Masayuki Ishikawa
a98650f609 arch: arm64: Remove unnecessary code in arm64_cpu_idle.S
Summary:
- I noticed that irq is enabled explicitly in arm64_cpu_idle.S
- The code is unnecessary since tasks, including the idle task,
  are created with irq enabled in up_initial_state()

Impact:
- Should be none

Testing:
- qemu-armv8a:netnsh_smp_hv with qemu-7.2.4

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2023-10-18 17:06:29 +08:00
zhangyuan21
48ca996ad7 arch: arm64 support smp function call
Add up_send_smp_call function to support smp function call.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-10-18 09:57:50 +08:00
zhangyuan21
21d9066c95 arm64: support up_coherent_dcache function
Before code is executed after being loaded into memory,
it is necessary to ensure the consistency of I and D cache.
The up_coherent_dcache function will flush the dache and
invalidate the icache to ensure cache consistency.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-10-16 16:08:23 +08:00
zhangyuan21
ca46cbb0bd arm64: target cpuid calculation error in arm64_gic_raise_sgi function
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-10-16 16:08:04 +08:00
TaiJuWu
1989749850 cpu_pause.c: fix typo
Signed-off-by: TaiJuWu <tjwu1217@gmail.com>
2023-10-14 00:26:31 -04:00
zhangyuan21
abfeafa876 arm64: XN should only be set when the attribute MT_EXECUTE_NEVER is set
Only when SCTLR_ELn.WXN is set to 1, regions that are writable at ELn
are treated as non-executable. Therefore, when SCTLR_ELn.WXN is set to
0, regions that are writable at ELn can be executed, so the writable
attribute cannot be used to restrict the executable attribute.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-10-13 22:48:13 +08:00
hujun5
cef8c598c7 arm64: Add support for FIQ interrupts
To compile arm64 NuttX, use the following command:
 ./tools/configure.sh -l qemu-armv8a:nsh_fiq
To run,use the following command
 qemu-system-aarch64 -cpu cortex-a53 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-10-12 16:56:24 -04:00
hujun5
061be5f18e refine: move BIT Macro to nuttx/bits.h
The BIT macro is widely used in NuttX,
and to achieve a unified strategy,
we have placed the implementation of the BIT macro
in bits.h to simplify code implementation.

Signed-off-by: hujun5 <hujun5@xiaomi.com>
2023-10-12 14:52:56 +08:00
Lee Lup Yuen
6cad7e9582 arm, arm64, xtensa, libxx: Change sed -r to sed -E to support macOS
When we build NuttX on macOS, it shows many `sed` messages (and the build still completes successfully):

```text
$ tools/configure.sh pinephone:nsh
$ make
sed: illegal option -- r
```

This is due to the Makefiles executing `sed -r` which is not a valid option on macOS.

This PR proposes to change `sed -r` to `sed -E` because:

- `sed -E` on macOS is equivalent to `sed -r` on Linux

- `sed -E` and `sed -r` are aliases according to the GNU `sed` Manual

- `sed -E` is already used in nuttx_add_romfs.cmake, nuttx_add_symtab.cmake and process_config.sh
2023-10-10 11:36:32 +03:00
Xiang Xiao
dfa0283d83 spinlock: Rename spin_islocked to spin_is_locked
align with Linux naming style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2023-10-06 20:03:19 -04:00
TaiJu Wu
ffba0d15a5 Feature: implement ticket spinlock
test config: ./tools/configure.sh -l qemu-armv8a:nsh_smp

Pass ostest

No matter big-endian or little-endian, ticket spinlock only check the
next and the owner is equal or not.

If they are equal, it means there is a task hold the lock or lock is
free.

Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>

Co-authored-by: Xiang Xiao <xiaoxiang781216@gmail.com>
2023-10-07 01:38:37 +08:00
wanggang26
7f5e6bd383 hostfs: mask bit fields of not support
Signed-off-by: wanggang26 <wanggang26@xiaomi.com>
2023-09-23 05:28:57 +09:00
raiden00pl
0e01836f09 serial: add an option that selects uart rpmsg as console 2023-09-22 19:46:26 +08:00
raiden00pl
3e79d21100 arch/arm: fix undefined reference to arm_serialinit when RTT console used 2023-09-21 20:30:27 +08:00
zhangyuan21
f47991e34d arch/arm64: select ARCH_HAVE_IRQTRIGGER for all arm64 chip
Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>
2023-09-20 20:52:03 +08:00
Shanmin Zhang
e8550a02b9 arm64: support reboot / poweroff for qemu virt arm64
Signed-off-by: Shanmin Zhang <zhangshanmin@xiaomi.com>
2023-09-20 00:40:44 +08:00
liaoao
3a08c0a1e6 qemu:fdt:add device tree support for goldfish arm/arm64
Signed-off-by: liaoao <liaoao@xiaomi.com>
2023-09-19 11:34:26 +08:00