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18609 Commits

Author SHA1 Message Date
Ville Juven
0a1a1e9b79 Fix user PGT flags (don't map them globally) 
A global mapping means it exists in all address environments. Only
kernel mappings should be mapped as global.
 2022-01-20 20:30:13 +08:00
Ville Juven
56ade25f31 Add pte getter to RISC-V MMU driver 
Like the title says, a getter to read one PTE.
 2022-01-20 20:30:13 +08:00
Ville Juven
c4b3672937 RISC-V MMU driver: fix region setting for L1/L2 page tables 
The region setting worked for L3 (Sv39) entries only. This fixes the
procedure so that L1 (Gigapages) or L2 (Megapages) can be also set
with it.
 2022-01-20 20:30:13 +08:00
Ville Juven
e676d2985d Present common MMU flags in common MMU driver header 
Flags to use for intermediate page tables, as well as leaf entries
 2022-01-20 20:30:13 +08:00
Ville Juven
33435e76da Changes to Sv39 MMU driver public header 
- Define RV_MMU_PT_LEVELS as the arch max
- Add way to find the PPN from a PTE
- Make utility function to create a satp register value, instead of
  combining this to mmu_enable
- Add function to read the current satp value
- Add function to write the satp register, also fix the fence instruction
 2022-01-20 20:30:13 +08:00
Ville Juven
926a19217e Add simple MMU driver for RISC-V (Sv39) 
Sv39 is the only mode supported for now. However, it should be trivial
to extend the driver to support the other modes (including Sv32) as well.

The driver is tested with mpfs only, but it should work with any riscv
implementation.
 2022-01-20 20:30:13 +08:00
Eero Nurkkala
133faf203d risc-v/mpfs: don't reset uart1 while entering OpenSBI 
u-boot/kernel may use any uart, not just uart1, depending
on the device tree configuration. They will also reset the
corresponding uarts as well. It doesn't need to be done
here.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-01-20 18:37:08 +08:00
Eero Nurkkala
54a4eb01ce risc-v/mpfs: avoid OpenSBI redefinition conflicts 
This drops the dependency to riscv_internal.h which ensures
less redefinition conflicts. OpenSBI declares some of the
variables again which are spread in many NuttX files.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-01-20 18:37:08 +08:00
Xiang Xiao
67fc54dd3d boards/sim: Change CONFIG_LIBCXX to CONFIG_HAVE_CXXINITIALIZE 
since the contructor is required with other libc++ implementation

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 16:20:41 +08:00
Xiang Xiao
af7fd718cc arch/sim: Don't add -lc++abi to STDLIBS 
link libs/libxx/libcxxabi instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 16:20:41 +08:00
YAMAMOTO Takashi
10f7ad85e6 arch/sim/src/nuttx-names.in: Add mprotect and sysconf 
For up_macho_init.c.
 2022-01-20 15:09:17 +08:00
YAMAMOTO Takashi
f0acf8e62a arch/sim/src/sim/up_macho_init.c: Add a workaround for Monterey 2022-01-20 15:09:17 +08:00
Petro Karashchenko
08043fb5bc net: unify FAR keyword usage for all net buffer memory mapped buffers 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-20 01:42:56 +08:00
Jukka Laitinen
fc3167b584 boards/riscv/mpfs: Remove reference to .vectors in linker scripts 
There is no such section. Instead, place the object mpfs_head.o at the start of
the text.

Put mpfs_head.o directly into the arch library; there is no need to define
it separately in HEAD_ASRC.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-01-20 01:37:34 +08:00
Jukka Laitinen
6428c1fdc4 arch/riscv/mpfs: Switch to use riscv_exception_common 
Clean up mpfs port by using the common code

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-01-20 01:37:34 +08:00
Jukka Laitinen
7b8eec3fa4 arch/risc-v/src/common/riscv_exception_common.S: Add support for > 2 CPUs 
Add a new configuration for CONFIG_N_IRQ_STACKS, whcih defaults to
CONFIG_SMP_NCPUS or 1
- this allows configuring multiple IRQ stacks also in the case where SMP
  support is not needed
- this is specifically needed in mpfs target, where "bootloader" build boots
  only on one hart, but the startup code executes on all harts and handles SW IRQs

Also don't store/restore GP if RISCV_SAVE_GP is not defined. If the GP is not
stored in fork, it can't be restored for new tasks

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-01-20 01:37:34 +08:00
Petro Karashchenko
767cf282c7 boards/arm/samv7: move HSMCI interface to common 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-20 01:24:14 +08:00
yinshengkai
face0514b6 touchscreen: update sim_touchscreen, using touch_upperhalf 
Signed-off-by: yinshengkai <yinshengkai@xiaomi.com>
 2022-01-20 01:22:25 +08:00
YAMAMOTO Takashi
a94c52b204 sim: Postpone constructor calls on macOS 
For Linux, we rename the section so that they are not invoked.
However, it doesn't work for macOS.

Notes:

* Renaming the sections (as the Linux version does) doesn't work
  because the section is looked by its flags, not by its names.

* No convenient tools available to alter the relevant bit in
  the section flags.

* The constructors are invoked before the program entry point.
 2022-01-20 01:16:56 +08:00
Daniel Agar
12c8a9626c stm32f7 serial fix PM_CONFIG build 2022-01-20 01:08:06 +08:00
zhuyanlin
793ec6c909 arch:xtensa:vectors:fix bugs in a0 save 
Use right EXCSAVE_X

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
zhuyanlin
a1a9ce3d1e arch:xtensa_panic: use right interrupt pointer in xtensa_panic 
When enable interrupt stack, use a12 instead of sp

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
zhuyanlin
88f5a209ce xtensa: move a3 save in handler instead of _xtensa_context_save 
As in _xtensa_syscall_handler, a3 was save and reused before
_xtensa_context_save, a3 save in _xtensa_context_save will generate
error.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
zhuyanlin
561fa88ed1 xtensa: add svcall handler 
svcall.c for xtensa

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
zhuyanlin
662f071d9a xtensa: fix svccall enter error 
1. error in A3 push stack
2. when interrupt stack enable, push a12 is xtensa_irq_dispatch
parameter 1, instead of sp. As sp is interrupt stack address set by
`setintstack`, not the interruptee stack address

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-19 16:28:03 +01:00
Petro Karashchenko
a6147109b1 arch/arm/src/armv6-m: fix typo 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-19 15:32:58 +01:00
Xiang Xiao
8bcdefafc9 board: Remove -fno-strength-reduce 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-19 00:14:03 +01:00
ligd
0a51f13ca5 rpmsg_rtc: merge the rpmsg_rtc_init to same place 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-01-18 22:48:15 +08:00
Petro Karashchenko
9551de7115 net: use HTONS, NTOHS, HTONL, NTOHL macro in kernel code 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-18 10:59:47 +01:00
Gustavo Henrique Nihei
04723a89f2 xtensa: Fix core voltage level when SPI Flash runs at 80Mhz 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-18 02:21:46 +08:00
raiden00pl
e140ba1a21 arch/stm32: fdcan cosmetics 2022-01-17 09:36:00 -03:00
raiden00pl
c450dea6e5 stm32: add FDCAN support 
based on PR #2987
 2022-01-17 09:36:00 -03:00
Petro Karashchenko
4f98ac4879 arch/arm/samv7: implement quadrature encoder driver 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-17 09:35:12 -03:00
zouboan
74aeb5d0c5 port nuttx to sparc-v8 commit 
includes following parts:
add support of sparc in arch/Kconfig
add support of sparc in boards/Kconfig
add sparc dir in arch, add sparc dir in boards
add support of sparc in libs/libc/machine
modify all the coding style problem about saprc
 2022-01-17 09:09:29 -03:00
Huang Qi
676d35f007 risc-v: Make exception_common 8 byte align 
Some SoC like bl602 require the exception entry 8 byte align, it should
be safe for other chips so we can apply it globally.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-17 11:44:50 +08:00
Huang Qi
e97ba17451 arch/risc-v: Refine riscv_cpupause.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-16 23:11:32 +08:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-16 11:11:14 -03:00
Xiang Xiao
41b9cf3cd8 rtc/rpmsg: Add sync parameter to control whether call clock_synchronize 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-16 11:58:13 +01:00
Xiang Xiao
93b0b9678f sim: Forward /dev/rtc0 operation to rpmsg rtc driver 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-16 11:58:13 +01:00
Huang Qi
3200c936cc arch/risc-v: Refine riscv_cpuindex.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-15 21:54:05 +08:00
Huang Qi
56a95ad0b5 risc-v: Remove ARCH_RV_ISA_[F|D] use ARCH_HAVE_FPU instead 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-15 11:42:01 +08:00
Huang Qi
5792d851e5 arch/risc-v/qemu-rv: Support both rv32/rv64 core 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-15 11:42:01 +08:00
Huang Qi
74cce59ac6 arch/risc-v: Make ISA configurable for qemu-rv32 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-15 11:42:01 +08:00
Alan C. Assis
dfd972a534 z80: Fix z80sim build system 2022-01-15 11:37:28 +08:00
chao.an
3544fc1fd6 risc-v/assert: add CURRENT_REGS check to avoid null pointer reference 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-01-15 02:20:01 +08:00
chao.an
c27839f98e arm/xtensa: save the running registers to xcp context 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-01-15 02:20:01 +08:00
Alexander Lunev
019fc0ad78 sim/netdev: eliminated RX data stream congestion in case of high TX network traffic. 
In case of high TX network traffic, netdriver_loop() that reads data from netdev
was invoked via up_idle() only after high TX network traffic had stopped.
That resulted in massive delay and drop of TCP ACK packets and
any other packets from netdev (tun/tap device).
 2022-01-14 19:39:39 +08:00
Eero Nurkkala
09bf8a5f89 risc-v/mpfs: mpfs_opensbi: fix fw_size calculation 
fw_start and fw_size were miscalculated. What was needed
was the pointed values of the offsets __mpfs_nuttx_start
and __mpfs_nuttx_end, not the values they had in place.

Also add the next_arg1 initialization.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-01-14 10:10:24 +01:00
Jukka Laitinen
122b907b91 arch/risc-v/src/mpfs/mpfs_opensbi_utils.S: Remove unncessary mv 
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-01-14 10:10:24 +01:00
Jari van Ewijk
3aed0aa641 S32K1XX: implement uniqueid 2022-01-13 15:34:47 -08:00
Huang Qi
6f1011a85e arch/risc-v: Rename bl602_entry.S to bl602_head.S 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-13 22:06:49 +01:00
Gustavo Henrique Nihei
c372e1e295 xtensa: Fix typo in xchal_cpX_store macros' invocation 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-13 21:07:04 +01:00
Huang Qi
7c93e96908 arch/risc-v: Fix typo in riscv_assert.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-13 14:53:18 +01:00
Huang Qi
3c15ae23cf arch/risc-v: Make __tarp_vec 4 byte align 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-13 14:53:18 +01:00
Huang Qi
c6749fd6fd arch/risc-v: Refine exception_common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-13 14:53:18 +01:00
Alan C. Assis
7b32849b84 esp32s2: Fix data cache option in menuconfig 2022-01-12 21:45:04 +01:00
Gustavo Henrique Nihei
80436dd7be xtensa/esp32s2: Fix some wrong definitions related to IRQ management 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-12 21:28:40 +01:00
Jari van Ewijk
0fc613f0b3 S32K1XX Reset Cause PROCFS: Add Kconfig option and cleanup 2022-01-13 01:29:42 +08:00
Huang Qi
e47a915f4c arch/risc-v: Refine riscv_vectors.S 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-12 18:53:01 +08:00
Xiang Xiao
1b77ae88ef fs/procfs: Remove the unnecessary strcmp 
since the procfs already make the same check for us

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-12 07:19:40 +01:00
Huang Qi
10bb48b9b4 arch/risc-v: Merge rv32im and rv64gc into common 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-11 23:24:33 +08:00
Gustavo Henrique Nihei
efca63e9e3 xtensa/esp32s2: Fix missing parenthesis on macro expression 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-11 23:21:13 +08:00
ligd
3cfc6761ff xtensa: fix lack of float register save & resotre 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-01-11 12:17:09 +01:00
Petro Karashchenko
a743fed63d file_operations: get back C89 compatible initializer 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-11 02:14:00 +08:00
Alan C. Assis
2079cc0f6e esp32: Add support to RS485 2022-01-10 10:49:16 +08:00
Petro Karashchenko
1fd51ccbe2 arch/arm/samv7: rework SAMv7 timer counter implementation 
There are two issues that are addressed with this change:
 - According to SAM E70/S70/V70/V71 Family datasheet the
   timer counter channels are 16-bit so timer counter
   value should be changed from uint32_t to uint16_t
 - The interrupt handling for timer counter channels can
   be simplified

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-09 17:43:31 +08:00
Xiang Xiao
bbf5511e3a arch/sim: Move the dummy ioe driver to drivers/ioexpender 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-09 11:06:06 +08:00
Xiang Xiao
b054bd9d37 arch/sim: Move the dummy foc driver to drivers/motor/foc 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-09 11:06:06 +08:00
Alan C. Assis
4ca38c6c50 esp32: Add PWM support using the LEDC peripheral 
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-08 14:46:51 +01:00
Petro Karashchenko
e7f9c7af21 typos: fix typos in Kconfig files 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-08 06:46:26 -03:00
Gustavo Henrique Nihei
73ea0c1627 xtensa: Improve Kconfig description of ESP32-S2 arch family 
Also fix the wrong "dual-core" statement, since all ESP32-S2 chips are
composed of a single Xtensa LX7 core.

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-07 22:25:05 +01:00
Xiang Xiao
3156a96a1b arch/sim: Move qspiflash simulation to drivers/spi instead 
since it's common implementation can be used in other arch too

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-07 23:50:11 +08:00
Xiang Xiao
d296f9c085 arch/sim: Move spiflash simulation to drivers/spi instead 
since it's common implementation can be used in other arch too

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-07 23:50:11 +08:00
ligd
ee916bdb91 CEVA: add ceva platform xc5 xm6 support 
Signed-off-by: ligd <liguiding1@xiaomi.com>
 2022-01-07 09:31:59 -03:00
Xiang Xiao
49c00e0361 arch/sim: Rename up_vfork[32|64].S to up_vfork_x86[_64].S 
to follow other arch/x86 arch/x86_64 convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-07 15:59:34 +08:00
Xiang Xiao
1a02556265 Revert "arch/sim: Rename up_vfork[32|64].S to up_vfork_x[32|64].S" 
This reverts commit 3982296294.
 2022-01-07 15:59:34 +08:00
chao.an
8c35d31808 Kconfig: Remove CONFIG_ prefix from config definition 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-01-07 13:16:18 +08:00
Xiang Xiao
3982296294 arch/sim: Rename up_vfork[32|64].S to up_vfork_x[32|64].S 
to align with up_vfork_arm.S naming style

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-06 09:42:44 +01:00
raiden00pl
6fe95d8314 stm32: add SocketCAN support, based on stm32_can.c 2022-01-05 06:16:41 -08:00
Zeng Zhaoxiu
fb43fd73ed signal: signal handler may cause task's state error 
For example, task is blocked by nxsem_wait(sem1), use nxsem_wait(sem2)
in signal handler, and take sem2 successfully, after exit from signal
handler to task, nxsem_wait(sem1) returns OK, but the correct result
should be -EINTR.

Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>
 2022-01-05 21:36:44 +09:00
raiden00pl
5b9b3814f8 stm32: add CAN error support 2022-01-05 18:33:06 +08:00
Jukka Laitinen
9aea5d5dbb arch/risc-v/src/mpfs/mpfs_serial.c: Correct setting of nbits 
Number of bits was set wrongly in TCSETS for mpfs

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
 2022-01-05 12:21:38 +08:00
Huang Qi
3a0e86c99b arch/risc-v: Replace __LP64__ with CONFIG_ARCH_RV64 
It can provide better auto complete experience for modern code editor,
since they use clang/gcc based parser to analyze code but lacks some
target dependent info such as __LP64__ for riscv64.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-04 23:22:43 +08:00
Eero Nurkkala
c87ae33459 risc-v/opensbi: update to version 1.0 
OpenSBI recently introduced version 1.0. Use the latest
version here as well.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
 2022-01-04 15:50:25 +08:00
Huang Qi
845168ce12 arch/risc-v: Refine riscv_assert.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-04 14:46:24 +08:00
Huang Qi
a6662c2887 arch/risc-v: Refine arch.h 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-04 14:46:24 +08:00
Abdelatif Guettouche
4edc5fb701 xtensa: Rename up_stack_color to xtensa_stack_color since it's an 
internal function.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
 2022-01-04 02:45:45 +08:00
Petro Karashchenko
4b190fbce1 arch/arm/samv7: correct number on interrupts 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-03 22:10:22 +08:00
Petro Karashchenko
6c2b40f98a typos: fix typos in many files 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-03 22:10:07 +08:00
Gustavo Henrique Nihei
c04fbb0365 risc-v/esp32c3: Sort LIBC_ARCH_* configs alphabetically 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-03 10:37:04 -03:00
Gustavo Henrique Nihei
78362b0949 xtensa/esp32: Use ROM implementations of libc functions 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-03 10:37:04 -03:00
Petro Karashchenko
c7d3a674fd drivers/sensors/as5048b: fix lower half init issue 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-03 11:38:44 +08:00
Xiang Xiao
d2309195da boards/sim: Add vncserver config for test 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-03 11:19:32 +08:00
Petro Karashchenko
d23ad9b9b0 userspace: fix typos in comments 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-02 20:50:30 +01:00
Huang Qi
b11e90f384 arch/risc-v: Refine riscv_initialstate.c 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-01-02 01:21:48 +08:00
Gustavo Henrique Nihei
c1fac720ec xtensa/esp32: Add missing param documentation for SPI Flash function 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
25f2dc2077 risc-v/esp32c3: Enable the creation of encrypted Flash partitions 
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
 2022-01-01 20:37:44 +08:00
Gustavo Henrique Nihei
9e5e60ba48 esp32s2/esp32c3: Build MCUboot bootloader with Flash Encryption support 2022-01-01 20:37:44 +08:00
Norman Rasmussen
185de258bf Fix preprocessing directives for uart flow control 
commit 58bd873729 had a mix of
`#if defined(X)` and `#ifdef X`, but used `#if X` in its TCSETS ioctl
logic which causes compile warnings.
 2021-12-31 18:51:17 +08:00
Dong Heng
c56c58020a risc-v/esp32c3: SPI flash MTD device uses all flash space 2021-12-31 11:40:23 +08:00