Commit Graph

18606 Commits

Author SHA1 Message Date
Xiang Xiao
f903a55102 sched/tcbinfo: Fix the compile warning
Update tcbinfo struct

armv8-m/arm_tcbinfo.c:109:3: warning: excess elements in struct initializer
  109 |   TCB_REG_OFF(REG_S31),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:109:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:110:3: warning: excess elements in struct initializer
  110 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:110:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:111:3: warning: excess elements in struct initializer
  111 |   TCB_REG_OFF(REG_FPSCR),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:111:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:112:3: warning: excess elements in struct initializer
  112 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:112:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:37:1: warning: missing braces around initializer [-Wmissing-braces]
   37 | {

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 17:36:27 +08:00
Ville Juven
4bd1bd177b RISC-V MMU: Add missing implementation for PTE getter
For some reason this was (mistakenly) left out from the patch
that was supposed to have it.
2022-01-27 10:22:30 +01:00
zhuyanlin
644c2be3aa armv7-a/r:cache: implemention clean&flush_dcache_all
For armv7-a/r cache:
And clean_dcache_all, flush_dcache_all

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 15:15:28 +08:00
zhuyanlin
1b08f607be arm/xtensa:cache: flush/clean dcache all if size large than cache size
For performance, if size large than cache size, use xxx_all instead

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
2022-01-27 15:15:28 +08:00
zhuyanlin
4d5c2586a9 armv7-a/r:cp15_invalidate_dcache_all: fix Sets mask error.
As NumSets field is bits 13-27, use 0x7fff instead.
And add way to get from CCSIDR.
2022-01-27 15:13:08 +08:00
Petro Karashchenko
311efcd180 arch/z80: fix garbage collector option to linker
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-26 16:50:59 +08:00
Petro Karashchenko
48211f90d3 ci: select ARMV7A_TOOLCHAIN_GNU_EABIL for ARMv7-A based builds
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-25 20:24:28 +08:00
Ville Juven
fc3cd308d5 Wipe the PMP configuration in MPFS bootloader start routine
This way old PMP configurations are removed upon warm reset.
2022-01-25 20:22:34 +08:00
Ville Juven
81188d9c94 Extend the RISC-V PMP functionality
- Add test for mode support, which is architecture dependent
- Add tests for address alignment and region size
- Add option to query for access rights
 - The function goes through every PMP entry and tests if an address
   range from [base, base+size] has been configured for desired
   access rights.
 - If several PMP entries match the range and access rights, the
   information is combined
 - End result is either no access, a partial match was found, or a full
   match was found. Details about the partial match are not provided.

The intent for testing access rights and not just blindly applying them
is a case where they are already set in e.g. a bootloader. In this
case, nothing should be done, unless the configuration does not match,
in which case the software must not continue further.
2022-01-25 20:22:34 +08:00
Ville Juven
8a4881c4e5 Implement CONFIG_BUILD_PROTECTED with MMU
NOTE: THIS ONLY WORKS WHEN KERNEL RUNS IN M-MODE FOR NOW

This frees the PMP for other use, e.g. HART memory separation.

The page tables are statically allocated, 1 per level.

This feature is now behind CONFIG_MPFS_USE_MMU_AS_MPU, because
only the MPFS target supports this (others are not tested).

If the MMU is used for memory separation within a HART, the PMP must
still be configured to allow user access to the memory mapped for the
HART, because PMP *rekoves* access by default. At this point all of
the user memory as well as the kernel RAM are opened.

A more flexible solution for PMP configuration will follow.
2022-01-25 20:22:34 +08:00
Ville Juven
7eb726d57f Add proper user/kernel space linker scripts for knsh target
The old implementation used the default ld.script for the kernel side
which did not obey the memory.ld limits whatsoever.

Also, provide the user space addresses from the linker script to get rid
of the pre-processor macros that define (incorrect) default values for
the user space composition.
2022-01-25 20:22:34 +08:00
Masayuki Ishikawa
7b1cf2dfac arch: arm: Fix make export for armv7-a SoCs
Summary:
- I noticed that make export does not work with swama5d4-ek:knsh
- This commit fixes this issue.
- NOTE: apps/Makefile also needs to be updated.

Impact:
- CONFIG_BUILD_KERNEL=y only

Testing:
- Build (make and make export) with sama5d4-ek:knsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
2022-01-25 11:05:22 +08:00
Jukka Laitinen
49085eebae arch/risc-v/src: Cleanups for opensbi
- remove some unneeded includes
- tab/space fixes
- change DEBUGPANIC to PANIC in noreturn function, otherwise it compiles only in DEBUG builds

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-25 00:10:46 +08:00
Jukka Laitinen
5bb3936212 arch/risc-v/src/opensbi: Update 3rd party opensbi version into Make.defs
This fixes build errors with more strict compiler settings

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-25 00:10:46 +08:00
Jukka Laitinen
8a6d62423d Revert "risc-v/mpfs: switch to NuttX types for opensbi"
This reverts commit d611e2d99b.
2022-01-25 00:10:46 +08:00
Eero Nurkkala
eb462a2eb3 risc-v/mpfs: configure harts according to CONFIG_MPFS_HART*_SBI
The following options need to be taken in account while determining
the proper hart_index2id -table:
  CONFIG_MPFS_HART1_SBI
  CONFIG_MPFS_HART1_SBI
  CONFIG_MPFS_HART3_SBI
  CONFIG_MPFS_HART4_SBI

Unused harts should be marked with -1. Hart0 is never used so it
stays at -1.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-24 23:25:53 +08:00
Huang Qi
71d3ff1045 arch/risc-v: Remove g_serial_ok
`WFI` is enough to wait the ready signal from master core,
so we can remove it.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-23 18:28:37 +08:00
Huang Qi
422e005183 arch/risc-v: Move xxx_cpustart.c to common
It's a common solution for MSIP and IPI based risc-v smp soc,
also works on qemu-rv smp (WIP).

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-23 18:28:37 +08:00
Norman Rasmussen
da5659138b Fix regression where used code was marked as unused
Commit 5d1a444812 replaced __attribute__
((unused)) with unused_code but two instances of __attribute__ ((used))
were also incorrectly replaced. Add used_code/used_data and used them
instead.
2022-01-23 14:57:19 +08:00
raiden00pl
4c2dd3924a include/nuttx/can.h: rename CAN_ERR_CTRL to CAN_ERR_CRTL for compatibility with libcanutils 2022-01-23 01:34:34 +08:00
Petro Karashchenko
6c27f3c19d toolchain: add libm to EXTRA_LIBS only if it is provided by the compiler
Some toolchains may be built without libm support, but using
such toochain should not generate any errors in case if math
functions are not used in the program

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-22 15:36:29 +08:00
Alexander Lunev
f73abc76d5 sim/netdev: retrieve all the queued RX frames from the network device on every poll.
As a result, the RX throughput is increased significantly w/o harming the TX throughput.
2022-01-22 15:34:58 +08:00
Xu Xingliang
021363f1db driver/mmcsd: add option to limit block count in multiple-block transfer mode.
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
2022-01-22 14:59:26 +08:00
Petro Karashchenko
d611e2d99b risc-v/mpfs: switch to NuttX types for opensbi
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-22 14:58:56 +08:00
Huang Qi
b803919b9d arch/risc-v: Merge mcause.h into irq.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-22 14:57:05 +08:00
Jukka Laitinen
9061c92ec8 arch/risc-v/src/mpfs: Make each hart entry configurable for bootloader
Add two config flags for each hart for a bootloader nuttx:

CONFIG_MPFS_HARTx_SBI :
- select whether the hart boots via opensbi or not.

CONFIG_MPFS_HARTx_ENTRYPOINT :
- the target address to jump to, either directly from startup code or
  from SBI if CONFIG_MPFS_HARTx_SBI is set

This allows building a nuttx based bootloader application, which can load
different applications/OSs for individual harts and jump to those

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-22 00:43:05 +08:00
Jukka Laitinen
36b73fd0a3 arch/risc-v/src/mpfs/mpfs_opensbi.c: Ensure stack alignment of 16 bytes
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
2022-01-22 00:43:05 +08:00
Eero Nurkkala
2a22c0e32d risc-v/mpfs: OpenSBI: utilize an index2id table
Hart index to hart id table is used to track unused and used harts. This
table is useful when configuring only some of the harts for OpenSBI use.
Mpfs will always have the hart0 unused, so mark it with -1.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
2022-01-21 13:40:58 -03:00
Abdelatif Guettouche
8c582c27b8 esp32c3_irq.c: Add a comment explaining the assigment of CURRENT_REGS to
regs.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-01-22 00:38:43 +08:00
Abdelatif Guettouche
e335d44028 esp32c3_irq.c: Skip over ECALL instruction.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
2022-01-22 00:38:43 +08:00
Petro Karashchenko
a32381ca32 Revert "risc-v/mpfs: switch to NuttX types for opensbi"
This reverts commit 1dccc374ab.
2022-01-21 21:38:31 +08:00
YAMAMOTO Takashi
f356ff34a7 arch/sim/src/sim/up_macho_init.c: Fix an assertion
Handle the case of no constructors.
2022-01-21 11:01:53 +01:00
Petro Karashchenko
1dccc374ab risc-v/mpfs: switch to NuttX types for opensbi
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
2022-01-21 17:12:22 +08:00
zouboan
0342272e5a up_progmem_erasesize for stm32f20xxf40xx_flash.c 2022-01-21 14:57:32 +08:00
Huang Qi
d846bb0235 arch/risc-v: Remove dupped irq code from mpfs
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
6dc4dd207f arch/risc-v: Remove dupped irq code from rv32m1
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
089dc2e090 arch/risc-v: Remove dupped irq code from litex
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
d1edd887d5 arch/risc-v: Remove dupped irq code from c906
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
bd57229f3c arch/risc-v: Remove dupped irq code from bl602
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
8532feda78 arch/risc-v: Remove dupped irq code from fe310
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
e81439a367 arch/risc-v: Remove dupped irq code from k210
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
7738bb98fc arch/risc-v: Remove dupped irq code from qemu-rv
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Huang Qi
f43d677c2e arch/risc-v: Unify common irq code to arch/irq.h
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2022-01-21 00:44:43 +08:00
Xiang Xiao
2935751bfd Fix error: implicit declaration of function 'up_cpu_index'
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Xiang Xiao
aa2cdcd848 xtensa/esp32: Change "cpu <= CONFIG_SMP_NCPUS" to "cpu < CONFIG_SMP_NCPUS"
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Xiang Xiao
77792a1598 sched: Define CONFIG_SMP_NCPUS to 1 in no SMP case
to simplify the SMP related code logic

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 23:21:21 +08:00
Xiang Xiao
04297c3ca3 board: Remove -fno-omit-frame-pointer from Make.defs
except sim arch, since this flag is set inside Toolschain.defs now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
2022-01-20 16:00:48 +01:00
Ville Juven
0a1a1e9b79 Fix user PGT flags (don't map them globally)
A global mapping means it exists in all address environments. Only
kernel mappings should be mapped as global.
2022-01-20 20:30:13 +08:00
Ville Juven
56ade25f31 Add pte getter to RISC-V MMU driver
Like the title says, a getter to read one PTE.
2022-01-20 20:30:13 +08:00
Ville Juven
c4b3672937 RISC-V MMU driver: fix region setting for L1/L2 page tables
The region setting worked for L3 (Sv39) entries only. This fixes the
procedure so that L1 (Gigapages) or L2 (Megapages) can be also set
with it.
2022-01-20 20:30:13 +08:00