lpc43/54 SDMMC: Wading through bits trying to make sense out of what is a event want interrupt which deal mostly with commands+responses and what is a data transfer event. DTO is the only wildcard. I think this clear now but DMA transfers will fail with CRC error.
lpc43/54 SDMMC: DTO is a wait event, not a transfer event.
lpc43/54 SDMMC: Significant simplication to previous design. More debug output.
lpc43/54 SDMMC: Don't allow duplicate events in waitmask and xfrmask.
lpc43/54 SDMMC: Not all interrupts were being disabled at the end of a transfer.
lpc43/54 SDMMC: Defer enabling DMA transfer interrupts until after command has been sent.
Squashed commit of the following:
arch/arm/src/lpc43xx: SDMMC driver now builds for the LPC43 (provided that the proper definitions appear in the board.h file).
arch/arm/src/lpc43xx: Update basic changes to the ported lpc54xx driver for lpc43xx clocking and GPIOs.
arch/arm/src/lpc43xx: Brings in the LPC54xx SD/MMC driver with absolutely no changes other than changing all occurences of 54 to 43.
arm/arm/src/lpc43xx: Add build support for the lpc54 SDMMC driver.
lpc54 SDMMC: Check for successful data transfer last. Checking first means that we miss errors.
Squashed commit of the following:
arch/arm/src/lpc54xx: SDMMC fixes.. DMA should not be enabled on non-DMA transfers, the burst setting in FIFOTH is supposed to match the burst setting in the BMOD reseters, Add DMA error interrupt support.
arch/arm/src/lpc54xx: Mostly costmetic changes to the SDMMC driver.
In lc823450, ldrex and strex are not supported. So we implemented
up_testset() with H/W Mutex. However, there was a bug in memory
access order. This change ensures correct memory access order in
up_testset() for lc823450.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
lc823450 http streaming
* arch/arm/src/lc823450: Use spinlock APIs in lc823450_gpio.c
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Add a warning message in up_ack_irq()
In SMP mode, H/W interrupts should be handled on CPU0 to avoid deadlocks.
Other changes:
Fix a potential race condition in up_enable_irq()
Use spinlock APIs instead of critical section APIs.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Enable HRT_TIMER in lc823450_timerisr.c
Other changes:
Fix style violations and call up_enable_irq() to assign CPU0 for IRQ handling.
Use spinlock APIs instead of critical section APIs.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Fix race conditions in dma/usbdev.
In SMP mode, critical data must be protected explicitly.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update README.txt
Add notes on .gdbinit and networking. Update comments on SMP.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update defconfigs
Enable HRT_TIMER, LC823450_MTM0_TICK, SPINLOCK_IRQ
Enable NET_TCP_RWND_CONTROL, NXPLAYER_HTTP_STREAMING_SUPPORT (rndis only)
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/lpc54xx: Adds the LPC54-specific clock configuration logic to the leveraged SD/MMC driver.
arch/arm/src/lpc54xx: Leveraged SD/MMC driver builds without error but is still missing clock configuration logic.
arch/arm/src/lpc54xx: Bring in LPC43xx SD/MMC driver from https://github.com/Smoothieware/smoothie-nuttx/tree/master/nuttx/arch/arm/src/lpc43xx
arch/arm/src/lpc54xx: LCD.. Fix some miconceptions about how the video address lines are used.
arch/arm/src/lpc54xx: Fix some LCD BPP and BRG vs RGB settings.
lc823450 smp improvement
* arch/arm/src/common: Apply irq_spin APIs to modifyregXX
Replace enter_critical_section with spin_lock_irqsave.
Replace leave_critical_section with spin_unlock_irqrestore.
Please see 6150299f54 as well.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Do not use modifyreg32() to enable Mutex.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Modify IRQ control for i2s
Interrupt will be handled on CPU0 with this change.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Apply irq_spin APIs to dma/syscontrol/usbdev.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Assign CPU1 to lpwork
This change will improve load balancing for networking with RNDIS.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* drivers/audio/wm8776.c: Improve stability in SMP mode
Apply irq_spin APIs to improbe performance.
Repeat to process a message to avoid deadlock.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Enable SPINLOCK_IRQ and NXPLAYER in rndis
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Squashed commit of the following:
arch/arm/src/lpc54xx: Finish off some missing logic. Complete now execpt for GPIO and LED support.
arch/arm/src/lpc54xx: Add lpc54_clrpend.c
arch/arm/src/lpc54xx: Serial driver is complete and compiles.
arch/arm/src/lpc54xx: Add beginning of a serial driver (still missing some logic)
arch/arm/src/lpc54xx: Fleshes out low level USART intialization.
arch/arm/src/lpc546xx/Kconfig: Add hooks to integrate with common seril upper half.
arch/arm/src/lpc54xx: Beginning of USART console support.
arch/arm/src/lpc54xx: Completes very basic clock configuration.
arch/arm/src/lpc54xx: Add clocking logic (still not complete)
arch/arm/src/lpc54xx: Beginning of PLL configuration logic.
arch/arm/src/lpc54xx: Fix a few things from first compile attempt. Compilation cannot work until I at least finish the clock configuration logic.
arch/arm/src/lpc54xx: Addes some SysTick logic.
arch/arm/src/lpc54xx: Completes basic startup logic (sans clock configuration) and interrupt configuration.
arch/arm/src/lpc54xx: Add generic ARMv7-M start-up logic (needs LPC54628 customizations); add emtpy file that will eventually hold the clock configuration logic.
arch/arm/src/lpc54xx: Add (incomplete) SYSCON register definition header file.
arch/arm/src/lpc54xx: Add FLEXCOMM header file.
arch/arm/src/lpc54xx: Bring in tickless clock logic from LPC43; configs/lpcxpresso-lpc54628: mount procfs if enabled.
arch/arm/src/lpc54xx: Add RIT clock definitions; add SysTick initialization (not finished)
LPC54xx and LPCXpresso-LPC54628: add more boilerplate files and stubbed out files.
arch/arm/src/lpc54xx: Add (incomplete) USART header file.
Add another condition to a Kconfig; refresh a defconfig.
arch/arm/src/lpc54xx/chip: Add LPC54628 memory map header files.
configs/lpcxpresso-lpc54628: Add basic build files for the LPCXpresso-LPC54628
arch/: Basic build directory structure for the LPC54628
arch/arm/src/xmc4/Kconfig: Define user friend I2C alias to follow other arch names
arch/arm/src/xmc4/Kconfig: Define user friend LIN alias to follow other arch names
arch/arm/src/xmc4/Kconfig: Define user friend I2S alias to follow other arch names
lc823450 smp audio
* arch/arm/src/lc823450: Remove a workaround in up_cpu_paused()
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Introduce g_gpio_lock to improve write performance in SMP mode.
NOTE: This is a tentative solution and should be replaced with more generic one.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* arch/arm/src/lc823450: Add a workaround in up_txready() to avoid data corruption.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Enable CONFIG_SMP for audio
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Update README.txt regarding SMP audio
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
1) The first enables building with CONFIG_ARCH_IDLE_CUSTOM enabled.
2) The second allows changing voltage output scaling setting and prevents enabling over-drive mode for low frequencies (STM32 F74xx, 75xx, 76xx, 77xx)
STM32, STM32 L4, and STM32 M4: USB OTGFS DMA trace output fix
STM32: Add dump buffer feature to stm32 F4 series
STM32 and STM32 L4: Fix bad USB OTGFS register address
STM32 L4: Fix typo in USB OTGFS register usage
STM32 L4: Add check in USB OTGFS driver to assure that SYSCFG is enabled
Nucleo-L496ZG: Make HSE on Nucleo-L496ZG default to enable USB
lc823450 auto LED support
* arch/arm/src/lc823450: Add auto LED for CPU activity
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
* configs/lc823450-xgevk: Add auto LED support
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
configs/stm32f429i-disco/ltdc: This configuration has been deleted because it violated the portable POSIX OS interface. It used apps/examples/ltdc and include ltdc.h and dma2d.h which were also removed for the same reason.
fs/userfs: This completes coding of the UserFS client and of the UserFS feature in general. This feature is being merged to main now because I believe it is innocuous. It is, however, untesed. The next step will be to develop a test case to verify the feature.
fs/userfs: Completes the request logic for the UserFS client. Still need the logic that receives the responses.
fs/userfs: Completes coding for most of the server side of the user filesystem logic.
fs/userfs: Big design changes, simplications. Use Unix domain local sockets instead of message queues. Easier to transfer big data in local sockets than message queues. Remove character drvier 'factory' it is not necessary.
fs/userfs: Minor reparitioning; volume private info does not need to be held on the OS client side.
libc/userfs: Add some of the server side logic.
fs/userfs: Add some UserFS initialization logic.
fs/userfs: Add frame work for the UserFS proxy. Remove all references to a block driver. There is no block dricer... what was I thinking?
fs/userfs: Add some initialization of the character driver, 'factory' device.
fs/userfs: Rename from fusefs to userfs to that we don't stomp on someone else's cool name.
Add a header file describing the fusefs interface.
Fix stm32 dmacapable on f20xx
* Fixed build for STM32F20XX platforms when CONFIG_STM32_DMACAPABLE is enabled
* Fixed build for STM32F20XX platforms when CONFIG_STM32_DMACAPABLE is enabled
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Port STM32F7 I2C driver to STM32L4
* arch/stm32l4: port STM32F7 I2C driver to STM32L4
STM32L4 I2C driver is in work-in-progress state (plentiful of
TODOs and #warnings) and lags many features found in more
up-to-date STM32 I2C drivers. The peripheral on STM32F7 and
STM32L4 are identical except for L4's 'wakeup from stop mode'
flag and STM32F7's I2C driver is in more 'ready to use' state.
Patch ports the STM32F7 I2C driver to STM32L4. The I2C clock
configuration is kept the same as before (I2CCLK = PCLK1 80 Mhz)
instead of switching to STM32F7 arch default that is I2CCLK=HSI.
Further work would be to add configuration option for choosing
I2C clock source instead of current hard-coded default.
* arch/arm/stm32f7: i2c: restore bus frequency after I2C reset
Copy frequency restoration fix from STM32L4 I2C driver to STM32F7 I2C driver.
* arch/arm/stm32f7: i2c: remove unused Kconfig option
* configs/nucleo-l496zg/nsh: enable I2C4 bus with i2ctool
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Master
* stm32_hrtim: fix warnings related with RCC
* stm32f33xxx_adc: add some publicly visable interfaces and some code to support injected channels
* stm32f33xxx_dma: add public interface to handle with DMA interrupts
* stm32_hrtim: change some names and add some coments
* chip/stm32f33xxx_adc.h: cosmetics
* nucleo-f334r8: add logic for zero latency high priority interrupts example
* stm32: update some ADC-related configuration in Kconfig
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM32L1, STM32L4 RTC: add periodic interrupts, update L1 RTC implementation
* STM32L4 RTC: add support experimental CONFIG_RTC_PERIODIC
* STM32 RTC: separate STM32L1 RTC into a separate file
STM32L1 RTC is very close to F4 or L4 versions, with two alarms
and periodic wakeup support so backported L4 peripheral to L1.
* RTC: add periodic alarms to upper and lower halves
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Master
* stm32f33xxx_adc.c: fix some warnings and compilation error when extsel not in use
* nucleo-f334r8/adc: change serial console to USART2 (STLINK COM)
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Lower part of STM32 CAN driver arch/arm/src/stm32/stm32_can.c uses all three hw tx mailboxes and clears TXFP bit in the CAN_MCR register (it means transmission order is defined by identifier and mailbox number).
This creates situation when order frames are put in upper part of CAN driver (via can_write) and order frames are sent on bus can be different (and I experience this in wild).
Since CAN driver API pretends to be "file like" I expect data to be read from fd the same order it is written. So I consider described behaviour to be a bug.
I propose either to set TXFP bit in the CAN_MCR register (FIFO transmit order) or to use only one mailbox.
Stm32 rtc small patches
* RTC: canceling an alarm marks it as inactive
* STM32L4, STM32F4, STM32F7 RTC: fix reading alarm value that is more than 24h in future
* STM32F0 RTC: fix backup register count in stm32_rtcc.h
All other STM32: SHIFTR_SUBFS_MASK was correct in STM32F0 only
* STM32L1: use correct EXTI line definitions
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Initial ADC support for the STM32F33XX
* stm32_adc.h: add JEXTSEL definitions and hrtim trigger configuration
* stm32_adc.c: move STM32F33 ADC logic to a separate file
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM32L4 small fixes to RTC
* STM32L4 RTC: init mode was never exited because nested locking in rtc_synchwait() disabled backup domain access
* STM32L4 RTC: use backup register magic value instead of INITS bit
The INITS (bit 4) of RTC_ISR register cannot be used to reliably
detect backup domain reset. This is because we can operate our
device without ever initializing the year field in the RTC calendar
if our application does not care about correct date being set.
Hardware also clears the bit when RTC date is set back to year 2000:
nsh> date -s "Jan 01 00:00:00 2001"
rtc_dumptime: Setting time:
rtc_dumptime: tm: 2001-01-01 00:00:00
rtc_dumpregs: New time setting:
rtc_dumpregs: TR: 00000000
rtc_dumpregs: DR: 00012101
rtc_dumpregs: CR: 00000000
rtc_dumpregs: ISR: 00000037
...
nsh> date -s "Jan 01 00:00:00 2000"
rtc_dumptime: Setting time:
rtc_dumptime: tm: 2000-01-01 00:00:00
rtc_dumpregs: New time setting:
rtc_dumpregs: TR: 00000000
rtc_dumpregs: DR: 0000c101
rtc_dumpregs: CR: 00000000
rtc_dumpregs: ISR: 00000027 <--- Bit 4 went missing!
...
This patch allows us to do:
stm32l4_pmstop(true);
/* Stop mode disables HSE/HSI/PLL and wake happens with default system
* clock. So reconfigure clocks early on Stop mode return.
*/
stm32l4_clockconfig();
without stm32l4_clockconfig() doing spurious and harmful backup domain
reset in rcc_resetbkp().
* STM32L4 RTC: put back the SSR race condition workaround
ST has confirmed that the issue has not been fixed, and that it applies
to STM32L4 too (was not in errata sheets due to documentation bug)
See discussion:
https://community.st.com/thread/43710-issue-with-rtc-maximum-time-resolution
* STM32F4, STM32L4, STM32F7 RTC: add more CONFIG_RTC_NALARMS > 1 to reduce code size
* STM32L4: rename stm32l4_rtcc.c to stm32l4_rtc.c to better match STM32F7
Cosmetic changes to comments
* STM32, STM32L4, STM32F7 RTC: stray comment and typos in chip/stm32_rtcc.h
* STM32L4 RTC: change maximum alarm time from 24h to one month
Approved-by: Gregory Nutt <gnutt@nuttx.org>
BCM2708: Add enough infrastructrue (more stubs) to get a clean compilation of the Pi Zero configuration (with many undefined things at link time).
BCM2708: Add basic interrupt handling logic
BCM2708: Add interrupt register definitions.
BCM2708: Add irq.h header file
BCM2708/Pi zero: bcm_boot.c and bcm_memorymap.h now compile. Added pizero linker script.
BCM2708/Pi Zero: Add Make.defs needed to build.
arch/arm/include/bcm2708, arch/arm/src/bcm2708, configs/pizero: Add some basic build and configuration logic.
configs/pizero: Add some basic structure of the Rasperry Pi Zero port.
Created directory configs/pizero. Nothing there now but a README.txt file.
Add initial boot.c and memorymap.c files
Author: Alan Carvalho de Assis <acassis@gmail.com>
Add AUX/UART/SPI registers definition
Author: Alan Carvalho de Assis <acassis@gmail.com>
Pizero GPIO registers
* Initial commit to add GPIO definitions
* Add remaining GPIO registers definition
Alan Carvalho de Assis <acassis@gmail.com>
BCM2708 memory map: Add VBASE defintions; fix VCSDRAM address per Alan; move all virtual address to the bottom of the file to avoid confusion -- top is all physical address; bottom is all veritural address.
Add initial memory map to BCM2708/BCM2835
Alan Carvalho de Assis <acassis@gmail.com>
Stm32, stm32l4 serial patches
* stm32: serial: add interface to get uart_dev_t by USART number, stm32_serial_get_uart
* stm32: serial: do not stop processing input in SW flow-control mode
* stm32l4: serial: do not stop processing input in SW flow-control mode
* stm32l4: serial: suspend serial for Stop mode
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Squashed commit of the following:
Change all calls to usleep() in the OS proper to calls to nxsig_usleep()
sched/signal: Add a new OS internal function nxsig_usleep() that is functionally equivalent to usleep() but does not cause a cancellaption point and does not modify the errno variable.
sched/signal: Add a new OS internal function nxsig_sleep() that is functionally equivalent to sleep() but does not cause a cancellaption point.
This commit backs out most of commit b4747286b1. That change was added because sem_wait() would sometimes cause cancellation points inappropriated. But with these recent changes, nxsem_wait() is used instead and it is not a cancellation point.
In the OS, all calls to sem_wait() changed to nxsem_wait(). nxsem_wait() does not return errors via errno so each place where nxsem_wait() is now called must not examine the errno variable.
In all OS functions (not libraries), change sem_wait() to nxsem_wait(). This will prevent the OS from creating bogus cancellation points and from modifying the per-task errno variable.
sched/semaphore: Add the function nxsem_wait(). This is a new internal OS interface. It is functionally equivalent to sem_wait() except that (1) it is not a cancellation point, and (2) it does not set the per-thread errno value on return.
sched/semaphore: Add nxsem_post() which is identical to sem_post() except that it never modifies the errno variable. Changed all references to sem_post in the OS to nxsem_post().
sched/semaphore: Add nxsem_destroy() which is identical to sem_destroy() except that it never modifies the errno variable. Changed all references to sem_destroy() in the OS to nxsem_destroy().
libc/semaphore and sched/semaphore: Add nxsem_getprotocol() and nxsem_setprotocola which are identical to sem_getprotocol() and set_setprotocol() except that they never modifies the errno variable. Changed all references to sem_setprotocol in the OS to nxsem_setprotocol(). sem_getprotocol() was not used in the OS
libc/semaphore: Add nxsem_getvalue() which is identical to sem_getvalue() except that it never modifies the errno variable. Changed all references to sem_getvalue in the OS to nxsem_getvalue().
sched/semaphore: Rename all internal private functions from sem_xyz to nxsem_xyz. The sem_ prefix is (will be) reserved only for the application semaphore interfaces.
libc/semaphore: Add nxsem_init() which is identical to sem_init() except that it never modifies the errno variable. Changed all references to sem_init in the OS to nxsem_init().
sched/semaphore: Rename sem_tickwait() to nxsem_tickwait() so that it is clear this is an internal OS function.
sched/semaphoate: Rename sem_reset() to nxsem_reset() so that it is clear this is an internal OS function.
STM32L4 RTC, PM: small fixes to subseconds handling, ADC power-management hooks
* STM32L4 ADC: add PM hooks from Motorola MDK
* STM32L4 RTC: add up_rtc_getdatetime_with_subseconds
* STM32 RTC: workaround for potential subseconds race condition
In all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to lock
the values in the higher-order calendar shadow registers until RTC_DR is read.
However many old chips have in their errata this silicon bug (at least F401xB/C,
F42xx, F43xx, L15xxE, L15xVD and likely others):
"When reading the calendar registers with BYPSHAD=0, the RTC_TR and RTC_DR
registers may not be locked after reading the RTC_SSR register. This happens
if the read operation is initiated one APB clock period before the shadow
registers are updated. This can result in a non-consistency of the three
registers. Similarly, RTC_DR register can be updated after reading the RTC_TR
register instead of being locked."
* STM32L4 RTC: correct RTC_SSR and RTC_TR read ordering
In all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to lock
the values in the higher-order calendar shadow registers until RTC_DR is read.
Change the register read ordering to match this and don't keep a workaround
for a hypothetical race condition (not in any L4 errata, lets for once assume
ST's silicon works as it is documented...)
* STM32L4 PM: remove useless #ifdefs and old non-L4 STM32 code
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM32, STM32 F7: LTDC and DMA2D drivers are not permitted to set the errno.
SIM LPC31xx: Serial and console drivers are not permitted to set the errno.
SAMv7, STM32, STM32 L4: DAC and ADC drivers are not permitted to set the errno.
STM32L4 FLASH, DFSDM: option bytes, JEXTSEL bits, ADC1 output to DFSDM chips change
* STM32L4 FLASH: add function for modifying device option bytes
* STM32L4 DFSDM: add JEXTSEL bits, ADC1 output to DFSDM chips change
ST's documentation hints that ADC output can be routed to DFSDM
on some STM32L4X3 chips, but I got confirmation from tech support
that this is just a documentation error so remove this from Kconfig.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
stm32:stm32f40xxx I2C ensure proper isr handling
Injecting data errors that causes a STOP to be perceived by the
driver, will continually re-enter the isr with SB not set and BTF
and RxNE set. This changes allows the interrupts to
be cleared and propagates a I2C_SR1_TIMEOUT to the waiting task.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
STM32L4 DFSDM: add peripheral, DAC, TIM: small changes
* STM32L4 DAC: do not configure output pin if it is not used
* STM32L4 TIM: fix compilation of timers with complementary outputs when not PWM_MULTICHAN
* STM32L4 DFSDM: peripheral for digital filters for sigma-delta ADCs
Initial version. Timer trigger support is not completed and there is
some issue with DMA.
Approved-by: Gregory Nutt <gnutt@nuttx.org>
Injecting data errors would cause the driver to
continually reenter the isr with BERR an RxNE.
This fix allows the error to be cleared and
propagated to the waiting task.
Injecting data errors would cause the driver to
continually reenter the isr with BERR an RxNE.
This fix allows the error to be cleared and
propagated to the waiting task.
STM32L4: ADC, Kconfig small changes
* STM32L4 ADC: port analog watchdog ioctls from the Motorola MDK
* STM32L4: Kconfig: add some L486 and L496 chips, remove duplicates
Approved-by: Gregory Nutt <gnutt@nuttx.org>
User should not be bothered by details like how many IP blocks there are. As no
current STM32L4 has second DAC block (channel 3), remove support for such
hypothetical hardware. DMA channels corrected.
Change-Id: I2cba7e55803871f1ff945538113f12cf5088f68d
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
Actually write something to the DAC DMA buffer.
Change-Id: I1b2516ac26fb17f5242611b56be8926c5f40c2c7
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
On a very memory constrained device with a single task. The
sem_wait and sem_post operations can be disabled, to save space.
The default is blocking enabled.
In the where CONFIG_SDIO_PREFLIGHT is not used and
dcache write-buffed mode is used (not write-through)
buffer alignment is required for DMA transfers because
a) arch_invalidate_dcache could lose buffered writes data
and b) arch_flush_dcache could corrupt adjacent memory if
the buffer and the bufflen, are not on ARMV7M_DCACHE_LINESIZE
boundaries.
In the case dcache write-buffed mode is used (not write-through)
buffer alignment is required for DMA transfers because
a) arch_invalidate_dcache could lose buffered writes data
and b) arch_flush_dcache could corrupt adjacent memory if
the maddr and the mend+1, the next next address are not on
ARMV7M_DCACHE_LINESIZE boundaries.
