Commit Graph

9 Commits

Author SHA1 Message Date
Dave Marples
d0cda60442 In the current implementation we only use very high priority interrupts (levels 0, 0x10 and 0x20 in CORTEX-M speak) but that means there are loads of lower priority ones that are effectively unused. I have *not* changed the semantics of these levels but have 'shifted' them to be based around the midpoint of the available interrupts (0x80) rather than at the top end....that allows for interrupts to be defined above (or, indeed, below) them as needed by the application. This should have no functional effect on existing code but adds in a clean capability to define higher priority interrupts. 2018-12-03 17:41:59 -06:00
Gregory Nutt
83bc1c97c3 Rename irqsave() and irqrestore() to up_irq_save() and up_irq_restore() 2016-02-14 16:11:25 -06:00
Gregory Nutt
f4115ab45c Correct LPC11xx priority definitions + fix some typos in comments 2016-01-25 07:36:26 -06:00
Gregory Nutt
0add2b8910 arch/arm/include/samv7: Add support for the SAME70 family 2015-11-14 11:36:21 -06:00
Gregory Nutt
348060f5d2 SAMV7: Add QSPI Register Definition Header File 2015-08-14 18:11:01 -06:00
Gregory Nutt
9b6c7661a4 SAMV7: Add TWI/I2C driver (untested) 2015-03-12 10:58:11 -06:00
Gregory Nutt
2571d6202d SAMV71-XULT: Add heap allocation logic 2015-03-07 11:46:54 -06:00
Gregory Nutt
67c21e6817 SAMV7 Kconfig: Add peripheral selections 2015-03-05 13:51:39 -06:00
Gregory Nutt
02e613b277 Add basic build directories and configuration logic for the SAMV7 family 2015-03-05 10:00:24 -06:00