Matrix.
This allows manipulating interrupts from both CPUs. Internal interrupts
however, still need to be disabled/enabled by each CPU.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
They do the same thing (manipulate interrupts) keeping them separated
was making things harder.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Allocating and attaching interrupts were both exported outside, however
these two move hand in hand and we don't have to expose these details.
Also, the parameters passed are saved and will be used to retrieve
information about the interrupt and the attached peripheral.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
interrupt.
That function will have a parameter to decide whether to allocate a
level sensitive interrupt or an edge sensitive interrupt.
All the drivers are also updated with this API change.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Ken Pettit is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
are do not go through the regular process where we attache the CPU
interrupt to a peripheral and update our map, also, they are fixed and a
have reserved CPU interrupt, thus hard code their values at startup.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
At this point we are in a critical section and have all the necessary
information to disable the interrupt properly (CPU, and CPU interrupt).
Leaving it to the drivers will complicate things as converting from IRQs
to CPU interrupts could be tricky in SMP mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This map also keeps track of the CPU that attached the IRQ. This will
be used to properly disable the interrupt in the correct CPU in SMP
mode.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA
This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals
In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code.
In AArch64, the frame pointer is stored in register X29.
Signed-off-by: chao.an <anchao@xiaomi.com>
ESP32 uses a different function to start the app CPU and no other xtensa
CPU uses this __cpu1_start function.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Gregory Nutt is the copyright holder for those files and he has submitted the
SGA as a result we can migrate the licenses to Apache.
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Consider follow coprocessor configuration case:
\#define XCHAL_CP_NUM 1 /* number of coprocessors */
\#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */
\#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */
\#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
\
\#define XCHAL_CP1_NAME "AudioEngineLX"
\#define XCHAL_CP1_IDENT AudioEngineLX
\#define XCHAL_CP1_SA_SIZE 208 /* size of state save area */
\#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */
\#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */
In this case, XTENSA_CP_ALLSET is 0x1, but valid coprocessors
bitmap is 0x2, use marco XCHAL_CP_MASK instead, it is bitmap of all
vaild coprocs.
Change-Id: I63ec01e4bd0cbafc62d56636cc11bdc4a2f7857f
