This change adds support for the following features:
- injected channels (default: 0)
- ADC resolution (default: 12bit)
- ADC low-level operations
- ADC external triggers
- custom ADC interrupts
- ADC sample time configuration
- configurable ADC SCAN mode (default on if DMA)
- configurable ADC DMA mode (default: one shot mode)
- reset the ADC block only if all ADC instances are closed
The L3 table address was calculated incorrectly. For every 2MiB of
mapped memory, an offset of 4KiB is needed from the base of the L3
table. The old calculation failed if paddr was not aligned to a 2MiB
boundary.
This change adds support for the following features:
1. PWM complementary outputs
2. interface for low-level PWM operations
3. support for all PWM channel modes
4. support for internal PWM channels (TIM1/TIM8)
5. support for PWM channel polarity and IDLE state
6. support for TRGO and BREAK
Kientis:edma Cleanup
Kinetis:EDMA Interrupt on last TCD
Kintis:edma remove dcache operations on passed data
Data can be chained in TCD and both read and write
can be in the chain. So the dmach ttype is not
relevent for all; the TCDs. Therefor we only perform
dcache operations on internal strutures, The caller
must perform dcache operations on their data.
kinetis:EDMA TCD Alignment of 32 Bytes to support Scatter/Gather
Summary:
- I noticed that ps shows incorrect stack usage when running
getprime in the background.
- With CONFIG_ARCH_ADDRENV=y, a user task including pthread
allocates its stack in the user space that needs to be
accessed with a correct address environment.
- This commit fixes this issue.
Impact:
- CONFIG_ARCH_ADDRENV=y only
Testing:
- Tested with sabre-6quad:knsh on qemu-6.2
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
RX_FIFO_ADDRs and TX_FIFO_ADDR were misconfigured. These addresses
overlapped causing data corruption during high USB loads. For
example, data corruption was present during the following conditions:
1. Composite USB driver was used (CDC/ACM + Mass storage)
2. /dev/ttyACM0 was accessed instantly from Linux side when
starting up.
3. Training data was sent to /dev/ttyACM0 from NuttX from the
very beginning periodically.
It was observed that while Mass storage was negotiating, sometimes
data sent from NuttX to Linux via CDC/ACM was corrupt, although it
was sent properly on the TX fifo.
Also, don't access TXCSRL_REG_EPN_TX_FIFO_NE_MASK for EP0 as it's
not applicable.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
ld: arch/libarch.a(cxd56_allocateheap.c.obj): in function `up_allocate_heap':
arch/arm/src/cxd56xx/cxd56_allocateheap.c:113: multiple definition of `up_allocate_heap'; arch/libarch.a(arm_allocateheap.c.obj):
arch/arm/src/common/arm_allocateheap.c:110: first defined here
Signed-off-by: chao.an <anchao@xiaomi.com>
arch/arm/src/common/arm_hostfs.c: In function 'host_read':
arch/arm/src/common/arm_hostfs.c:156:24:
warning: passing argument 1 of 'up_invalidate_dcache' makes integer from pointer without a cast [-Wint-conversion]
156 | up_invalidate_dcache(buf, buf + count);
| ^~~
| |
| void *
In file included from arch/arm/src/common/arm_hostfs.c:26:
include/nuttx/cache.h:261:37: note: expected 'uintptr_t' {aka 'unsigned int'} but argument is of type 'void *'
261 | void up_invalidate_dcache(uintptr_t start, uintptr_t end);
| ~~~~~~~~~~^~~~~
Signed-off-by: chao.an <anchao@xiaomi.com>
Initialize .domains_init function entry point in sbi_platform_operations when
CONFIG_OPENSBI_DOMAINS=y. In this case, the board specific code must provide
the "board_domains_init" function.
Signed-off-by: Jouni Ukkonen <jouni.ukkonen@unikie.com>
- Introduce the ESP32_WIFI option to replace the broader
ESP32_WIRELESS option. ESP32_WIRELESS is used by both WIFI and BLE.
- Move common functions from esp32_wifi_adapter to esp32_wireless.
- Change the order of including the external libraries to avoid undefined references.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit adds RX DMA support to serial driver. The DMA is currently
supported only for USART peripherals, not for UART. It uses two circular
buffers which size can be setup by SAMV7_SERIAL_RXDMA_BUFFER option.
The idle bus interrupt is enabled to ensures data are read even if the
buffer is not yet full. The timeout can be setup by
SAMV7_SERIAL_DMA_TIMEOUT option.
This adds support only for RX transfers.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit adds functions sam_dmarxsetup_circular() and
sam_dmarxstart_circular() that create API for operating with two or more
circular buffers. This can be used for DMA operation with serial driver
or ADC where ping pong buffers are required to successfully transfer the
data at high speed.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit enhances SAMV7 serial driver with RS-485 mode available to
USART peripherals. The hardware automatically sets RTS pin high when
data are transfered and low then no transfer occurs. Only USART peripherals
support this mode, UART peripherals do not.
This mode can be enabled by configuration option SAMV7_USARTx_RS485MODE.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Summary:
- Since the stack coloration is done for every 32bits
this function should be done in the same way.
Impact:
- None
Testing:
- Tested with qemu-a53:nsh
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
N/A
Summary:
Arm64 support for NuttX, Features supported:
1. Cortex-a53 single core and SMP support: it's can run into nsh shell at
qemu virt machine.
2. qemu-a53 board configuration support: it's only for evaluate propose
3. FPU support for armv8-a: FPU context switching at NEON/floating-point
TRAP is supported.
4. psci interface, armv8 cache operation(data cache) and smccc support.
5. fix mass code style issue, thank for @xiaoxiang781216, @hartmannathan @pkarashchenko
Please refer to boards/arm64/qemu/qemu-a53/README.txt for detail
Note:
1. GCC MACOS issue
The GCC 11.2 toolchain for MACOS may get crash while compiling
float operation function, the following link describe the issue
and give analyse at the issue:
https://bugs.linaro.org/show_bug.cgi?id=5825
it's seem GCC give a wrong instruction at certain machine which
without architecture features
the new toolchain is not available still, so just disable the MACOS
cibuild check at present
Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
1. Fix error recovery mechanism during transmission error
handling (enable transmission at the end).
2. Fix compilation / operation with CONFIG_SAMV7_EMAC_PREALLOCATE=y
3. Enable fully configured address space for transmission queues
to allow sending packets with length more than 976 bytes. With
partially configured address space the AHB error is generated
during transmission of long packets.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
With faster data transfer rates, it was seen that the read
requests occasionally were issued while the USB RX operation
was actually in progress. This patch makes sure the system
doesn't accidentally read the RX fifo while it's being filled
up, but rather, checks for the RXCSRL_REG_EPN_RX_PKT_RDY_MASK
flag. This flag indicates the packet is ready to be read.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
cache_dbus_mmu_set and cache_ibus_mmu_set return positive values in case
of errors, so DEBUVERIFY could never detect them since this macro checks
for negative values.
Besides, the successful execution of those functions is mandatory for
the reliable operation under Protected Mode, so the verification is
always performed, even when DEBUG is not enabled.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
forget to update in this patch:
commit b02db04e00
Author: Xiang Xiao <xiaoxiang@xiaomi.com>
Date: Sun Jun 5 17:10:19 2022 +0800
arch/assert: Keep the thread dump column order same as ps
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
1.Move __XSTR from include/arch.h to include/irq.h
2.Move FLOAD/FSTORE and REGLOAD/REGSTORE from include/arch.h to src/common/riscv_internal.h
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
* arch/arm/src/tiva/common/tiva_lowputc.c
(tiva_lowsetup):
For each UART, if Kconfig enables RTS/CTS (e.g.,
CONFIG_UART0_IFLOWCONTROL and/or CONFIG_UART0_OFLOWCONTROL),
configure the corresponding GPIO(s).
* arch/arm/src/tiva/common/tiva_serial.c:
(struct up_dev_s):
If CONFIG_SERIAL_IFLOWCONTROL, add a bool field 'iflow'. If
CONFIG_SERIAL_OFLOWCONTROL, add a bool field 'oflow'. This is
inspired by the implementation for kinetis.
(g_uart0priv, g_uart1priv, g_uart2priv, g_uart3priv, g_uart4priv,
g_uart5priv, g_uart6priv, g_uart7priv):
If Kconfig enables RTS/CTS for a UART (e.g.,
CONFIG_UART0_IFLOWCONTROL thru CONFIG_UART7_OFLOWCONTROL), set
the corresponding iflow and/or oflow flag(s).
(up_setup):
Check the above-mentioned iflow and oflow flags and set or unset
the RTSEN and/or CTSEN bits in the UART's CTL register to enable
the feature.
The "p" format specifier already prepends the pointer address with "0x"
when printing.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Sync driver interfaces, also fixes the handling of special pin value for
esp32s2_gpio_matrix_in and esp32s2_gpio_matrix_out functions
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Starting the rptun with the autostart flag set will cause significant
delays at the boot, as it will wait for the master to be up. U-boot/linux
combination may take more than 10 seconds to boot to the point where the
rpmsg bus is initialized.
For now, the user needs to initialize the rptun separately, for example,
by issuing the following command:
rptun start /dev/rptun/mpfs-ihc
This command will also block if started before the rpmsg bus master is up.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Move the linker defined symbols to a separate file, so they can be
accessed without pulling in everything from riscv_internal.h and
whatever it includes (e.g. syscall.h drags in a lot).
SAMA5D2 and SAMA5D4 does not support external reset.
Some SAMA5 board's Kconfig contain item SAMA5_SYSTEMRESET, but it is better in arch/arm/src/Kconfig.
Add a function to easily enable event handling on fabric and mss gpios. This
is similar to what exists e.g. for stm32 arm chips.
Also fix some small bugs in mpfs_configgpio related to IRQ bits configuration
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This patch fixes the following issues:
1. MPFS_EMMCSD_HRS06_EMM bitmask had to be 0x7, not 0x03
2. putreg32() caused outright memory corruption as the
arguments were in wrong order
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
When using HSE to clock RTC NuttX internal time is gaining 5.5 second per
minute. Problem was NuttX using 7182 for one of the RTC division factors,
it should have been 7812. The incorrect factors used are 7182 and 0xff.
These are used in 3-4 places within Nuttx and other places as 7812 and 0xff.
However, the STMicro app note AN4759 suggests using 7999 and 124, which is
what I've used.
Explanation: These 2 factors are used to divide the HSE clock (which at this
point is 1 MHz) to 1 Hz for the RTC hardware.
To test the 2 factors, add 1 to both numbers and multiply them together.
The result needs to be as close as possible to 1 MHz.
The suggested values of 7999 and 124 => 8000*125 = 1,000,000, the prime
factors. So, the best fix for Nuttx would be these values.
Issue discovered and fixed by Peter Moody
In order to support multiple LCD instances per board, add a pointer from
lcd_planeinfo_s to the lcd_dev_s which it belongs to. Also enhance the
putrun, getrun, putarea and getarea methods to pass through the
lcd_dev_s pointer to the respective device driver.
Port all LCD device drivers to this lcd_planeinfo_s extension.
Enhance SSD1306 driver to support multiple LCDs.
Signed-off-by: Michael Jung <michael.jung@secore.ly>
The old implementation needed a contiguous memory block for user
ROM/RAM. This is because there was only 1 L3 page table which can only
map a contiguous memory area.
Also, remove the PMP configuration which just complicates things,
rely on the MMU mappings instead.
Update PLL configuration parameters to match the values provided
by the vendor.
Also remove extra call to mpfs_pll_config() as it's already called
at mpfs_clockconfig().
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This patch adds corrected implementation of FLASH memory to be used
with progmem driver for use with mtd filesystems like nxffs or smartfs.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
Summary:
- I noticed that QEMU shows a high CPU load.
- This commit re-adds imx_idle.c to avoid this issue.
Impact:
- None
Testing:
- Tested with sabre-6quad:smp with QEMU
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This patch implements working support for EXTI GPIO.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
--
v1 -> v2:
Suggested by: Petro Karashchenko
- change (1 << n) to (1 << (n)) in macro definition
- change 1 << X to (1 << X) in code
- fix alignment
v2 -> v3:
Suggested by: Petro Karashchenko
- I was supposed to change (1 << pin) to 1 << pin, not the other way around:)
Summary:
- I noticed that sometimes uart shows nothing on the maix-bit board.
- This commit adds a workaround to avoid such the issue
Impact:
- k210 only
Testing:
- Tested with maix-bit
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This provides USB composite (CDC/ACM and Mass Storage) support
for mpfs board. In addition, a number of USB fixes are included:
- Support for Setup Out packets
- Proper support for larger than packet size writes
- Finishing setup packets properly
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Output "X" with showprogress and make a system reset.
Silently ignoring failed training is dangerous and will cause random behaviour if DDR is used
Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This patch adds new chip family, stm32wl5x. This is bare minimum
implementation of said chip. I've tested this by running nsh.
There are only two chips in this family, stm32wl55 and stm32wl54.
The only difference between them is that stm32wl55 has LORA.
stm32wl5 is dual CPU (not core!). Right now only CPU1 is implemented.
CPU0 has access to radio hardware (while CPU1 does not). Chip is
designed so that CPU0 handles radio traffic while CPU1 does the
heavy lifting with data - there is communication pipe between two
CPUs.
I plan to use nuttx on CPU1 and LORA from stm32cube on CPU0 so I
don't have implementing CPU0 right now - once we have working LORA
in nuttx this may change.
Peripherals (except for radio) are shared so it's best to focus on
CPU1 to initialize all peripherals so that CPU0 can only use them
later. There is no real benefit to implement CPU0 if we don't have
working LORA/radio support in nuttx.
In time I will be implementing more and more things from this chip.
Right now I would like this minimal implementation to be merged in
case someone wants to work on this chip as well.
Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl>
---
patch v1->v2
- fixed formatting (suggested by Alan Carvalho de Assis)
- rebased patch to master (previous patch was based on nuttx-10.2
and did not compile on master)
arch/x86/Kconfig:28:warning: choice value used outside its choice group
arch/x86/Kconfig:29:warning: defaults for choice values not supported
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
We might have a situation where an allocation will be requested before
the call to `up_initialize` is performed. For the current code, this
situation is the stack for the CPUs in SMP mode.
Beside this issue, it's natural to have the internal heap initialized
with the other heaps.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
jumping back to the assembly signal trampoline and getting into its
infinite loop.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Change pin initialization timing for camera from board power on to camera device
power on for the following purposes.
- avoid unnecessary power consumption
- Make the corresponding pins available for other uses when camera is not in use
RF and system timer interrupt are used for ble.
tlsr82_flash.c:
1. BLE will loss packets during flash operation beacause the interrupt
is disabled and the operation take too long (especially erasing,
about 100ms), so allow RF and system timer interrupt during flash
operation;
2. Add sched_lock()/sched_unlock() to avoid the task switch in ble and
system timer interrupt;
flash_boot_ble.ld:
3. Because of 1, the code executes in RF and system timer interrupt
must be in ram to avoid bus error. The sem_post() will be called and
const variable g_tasklisttable will be accessed in RF and system
timer interrupt handler;
4. To improve the performance, copy some frequently called function to
ram as well, such as: sem_take(), sched_lock(), sched_unlock(),
some lib functions, some zephyr ble functions and some tinycrypt
functions;
5. The RF and system timer interrupt handler will call some libgcc
functions, so copy all the libgcc functions to ram exclude _divdi3.o,
_udivdi3.o and _umoddi3.o;
tlsr82_serial.c
6. Make up_putc() be thread safe, add enter/leave_critical_section() in
function uart_send_byte();
tc32_doirq.c
7. Increase the RF and system timer interrupt response priority;
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
since the code could map the unsupported work to the
supported one and remove select SCHED_WORKQUEUE from
Kconfig since SCHED_[L|H]PWORK already do the selection
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
As coproc_save/restore only used in context_restore/save.
Use macro instead of function.
Some register use optimize.
Unify with arm/riscv.
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
The current SAMv7 PWM driver assumes that all PWM channels should
work in sync mode, but that is a partial case of a generic PWM
driver operation.
Start SAMv7 PWM channels in async mode. The sync mode should be
implemeted either using ioctl command or via a separate Kconfig
option.
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Linux kernel uses M-mode trap for handling Inter-Hart Communication (IHC).
This patch provides all the required functionalities for this purpose.
Previously, HSS bootloader was required. Now, NuttX is run as the
bootloader providing OpenSBI vendor extensions instead. This setup has
been tested on the following configuration:
- Hart 0 has NuttX in bootloader mode with OpenSBI
- Hart 1 unused
- Hart 2 has NuttX configured at 0xa2000000
- Hart 3 has U-boot / Linux kernel (at 0x80200000)
- Hart 4 has U-boot / Linux kernel (at 0x80200000)
Upon startup, NuttX on hart 0 will initialize SD-card driver, loads
the hart 2 NuttX from the SD-card and loads the U-boot to 0x80200000.
Also the nuttx.sbi -binary is loaded from SD-card into address 0x80000000,
which is also marked as reserved area in the Linux kernel device tree (for
the chuck 0x80000000 - 0x80200000).
Hart 2 NuttX waits until Linux kernel (IHC master) is started. After the
initial handshake, RPMsg / virtIO bus along with the IHC may be used for
proper AMP mode.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
