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14470 Commits

Author SHA1 Message Date
Anthony Merlino
30f6dbc613 Throw compile time error if tickless timer is set to TIM6/TIM7 2022-03-28 00:33:26 +08:00
Anthony Merlino
95199f4790 stm32h7 timer: Clean up some bit operations to make them more readable. 2022-03-28 00:33:26 +08:00
Anthony Merlino
e5c8bb9b34 stm32h7: Fix a bunch of tickless issues. 2022-03-28 00:33:26 +08:00
Anthony Merlino
2fad06008a stm32h7: Adds tickless support. 2022-03-28 00:33:26 +08:00
ligd
f623ac0f13 armv7-m/armv8-m: move up_pref* api to common place 
Signed-off-by: ligd <liguiding1@xiaomi.com>
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-26 13:39:18 +02:00
Huang Qi
9cffc105c8 arch: Show assigned cpu in dump task 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-23 22:18:15 +08:00
chao.an
7b73606300 arm/schedulesigaction: update the SP to signal context top 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-23 19:08:37 +09:00
chao.an
a770ff2017 arm/vfork: update the SP to stack top 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-23 19:08:37 +09:00
Xiang Xiao
9ae0dcd4a2 arch/arm: Remove the code copy register from xcpt to stack 
since xcpt always point to the stack after the below change:
commit 7b9978883c
Author: chao.an <anchao@xiaomi.com>
Date:   Tue Mar 1 01:06:24 2022 +0800

    arch/arm: optimize context switch speed

    The current context save implementation saves registers of each task
    to xcp context, which is unnecessary because most of the arm registers are
    already saved in the task stack, this commit replace the xcp context with
    stack context to improve context switching performance and reduce the tcb
    space occupation of tcb instance.

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-23 19:08:37 +09:00
Petro Karashchenko
68902d8732 pid_t: unify usage of special task IDs 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-22 21:22:32 +08:00
Harri Luhtala
2ee12b2c5d arch/arm/src/stm32l4: peripheral voltage monitor support for vddio2 
Signed-off-by: Harri Luhtala <harri.luhtala@haltian.com>
 2022-03-22 21:08:29 +08:00
Petro Karashchenko
757d01d915 progmem: eliminate PROGMEM_ERASESTATE configuration option 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-22 10:01:41 -03:00
smartether
7fbadb5c16 fixed mpu9250 not work on i2c bus issue. 
1,set rp2040 FIFO_MAX_SIZE to 16.ref: pico sdk ->
static inline size_t i2c_get_write_available(i2c_inst_t *i2c) {
const size_t IC_TX_BUFFER_DEPTH = 16;
return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr;
}
 2022-03-21 12:07:03 +08:00
Petro Karashchenko
3fff4508c7 netinitialize: call xxx_netinitialize unconditionally 
The xxx_netinitialize is defined to a function only if
CONFIG_NET=y and CONFIG_NETDEV_LATEINIT=n.  Otherwise it
is defined to an empty macro.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-19 17:41:33 +08:00
Huang Qi
edef327655 arch/arm: Move ARCHCPUFLAGS to Toolchain.defs 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-19 02:24:00 +08:00
Petro Karashchenko
c1fb14ccaa boards/arm/samv7/same70-qmtech: add /dev/timer0 support 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-19 02:21:03 +08:00
wangbowen6
7de7ba1b7e phy62xx_exception: using armv6-m exception_common code. 
Signed-off-by: wangbowen6 <wangbowen6@xiaomi.com>
 2022-03-18 20:01:00 +08:00
chao.an
19119a9c43 arch/arm: set the SP to stack top 
fix the stack imbalance

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-18 07:56:51 +09:00
Petro Karashchenko
c3bae60c57 drivers/can: optimize can driver reader side 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-17 15:43:15 +08:00
SPRESENSE
c05ace557f arch: cxd56xx: Fix critical section in serial transmission 
Fix an issue that the serial transmission buffers are corrupted because
serial transmission are not protected by critical section in non-smp mode.
 2022-03-16 20:23:41 +09:00
Petro Karashchenko
985829190e arch/arm/samv7/sam_tc: implement timer driver support 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-16 03:19:57 +08:00
Matthew Trescott
8c471db932 Corrections to Tiva KConfig 2022-03-15 11:32:31 -04:00
Matthew Trescott
bc80bbddc7 Add Tiva CAN driver 2022-03-15 11:32:31 -04:00
chao.an
81130bc692 arch/arm: remove unused arm_copyfullstate/arm_copyarmstate 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-15 23:03:51 +09:00
chao.an
7b9978883c arch/arm: optimize context switch speed 
The current context save implementation saves registers of each task
to xcp context, which is unnecessary because most of the arm registers are
already saved in the task stack, this commit replace the xcp context with
stack context to improve context switching performance and reduce the tcb
space occupation of tcb instance.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-15 23:03:51 +09:00
Petro Karashchenko
b04447d066 timer_lowerhalf: minor improvements 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-15 10:30:48 +08:00
Xiang Xiao
b6bc460b2c arch: Make the comment and definition of CONFIG_SYS_RESERVED correctly 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 22:51:00 +02:00
chao.an
ea42981cc6 syscall/names: export the syscall name in STUB module 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 21:37:53 +02:00
chao.an
d398ffb930 arm/armv7-a/r: unified syscall registers dump 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 21:37:53 +02:00
chao.an
7c02432f0e arm/armv7-a/r: set the default CPU mode to System 
In SVC mode, the banked register will be inconsistent with the user mode register:

arch/arm/src/armv7-a/arm_vectors.S

 276   .globl  arm_syscall
 277   .globl  arm_vectorsvc
 278   .type arm_vectorsvc, %function
 279
 280 arm_vectorsvc:
...
 286   sub   sp, sp, #XCPTCONTEXT_SIZE        // < SVC mode SP
...
 308   stmia   r0, {r13, r14}^                // < USR mode SP/LR
...

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[    2.200000] [ 4] [ ALERT]   R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710
[    2.200000] [ 4] [ ALERT] CPSR: 00000073
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 1 80202018 1 80202018 0 0 0 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 802027d0 1080f710 80001229
[    2.200000] [ 4] [ ALERT] CPSR: 00000070

SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[    2.200000] [ 4] [ ALERT]   R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2
[    2.200000] [ 4] [ ALERT] CPSR: 00000070
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 2b 0 80202780 0 0 0 0 80202710
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 10843d80 800039d5 10801425
[    2.200000] [ 4] [ ALERT] CPSR: 00000073

SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode

This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall.

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-14 19:54:53 +09:00
Xiang Xiao
54e630e14d arch: Merge up_arch.h into up_internal.h 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-14 09:32:17 +02:00
Xiang Xiao
c96c96a399 drivers: Merge the common driver initialization into one place 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-13 11:24:48 -03:00
Xiang Xiao
39fb09738d arch: Move [arm|xtensa]_intstack_[alloc|top] to common header file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-11 23:08:07 +02:00
Xiang Xiao
17d1a48fc9 arch: Remove up_puts prototype from up_inernal.h 
since it's defined in include/nuttx/arch.h now

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-11 23:08:07 +02:00
Petro Karashchenko
fc9e2d272e arch/arm/arm[-a|-r]: fix typos in comments 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-03-11 11:08:01 +08:00
Xiang Xiao
29cb85ba17 arch/stm32: Fix compiler warning 
chip/stm32_i2s.c:1949:12: error: conflicting types for built-in function 'roundf'; expected 'float(float)' [-Werror=builtin-declaration-mismatch]
 1949 | static int roundf(float num)
      |            ^~~~~~

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-10 19:46:01 +02:00
Xiang Xiao
a07dc2363e c5471/c5471_irq.c: Fix error: '__builtin_memcpy' forming offset [4, 31] is out of the bounds [0, 4] of object '_svectors' with type 'int' 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-10 19:46:01 +02:00
Huang Qi
69cfe8d626 arch/arm: Support setjmp/longjmp for all socs 
After check the official specification of ARM ISA
and Thumb ISA, the arch_setjmp_thumb.S are written
by arm unified assembly language,
so it easy to make it works for ARM and thumb ISA.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-09 17:13:21 +02:00
Richard Tucker
4888be37e3 arch/arm/src/sam34/sam_dmac.c: Fix compilation error 2022-03-09 10:18:32 +08:00
Huang Qi
bfedbf1c05 arm/imx6: Enable setjmp test in ostest 
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-08 21:00:29 +08:00
Huang Qi
cfff115f21 arm: Move setjmp to common place 
Since some Cortex A core supports thumb mode also,
thus they can share same implementation.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-03-08 21:00:29 +08:00
Juha Niskanen
779665c704 arch/arm/src/stm32l4: STM32L4+ might need flash data cache corruption workaround 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2022-03-04 14:00:20 +08:00
Oleg Evseev
625d230d28 arch/arm/src/stm32f7/stm32_can.c: fix CAN3 receiving 
by fixing filter initialization.

STM32F7 CAN3 works in single peripheral configuration and there is only 14 filter banks: 0-13. Previously not available 14 indexed filter (CAN_NFILTERS/2) was wrongly used for for receiving to FIFO. Now zero indexed filter is correctly used instead.
 2022-03-03 14:31:37 -03:00
zhuyanlin
5af1b671b6 armv7-a/armv7-r:cache: modify hardcode in cache set/way operation 
Some chip not use the default cache size & way , read from
CCSIDR instead of hardcode.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-03-03 14:11:31 +08:00
Masayuki Ishikawa
2a434fe1fa arch: imx6: Add the pgheap for imx6 
Summary:
- This commit adds the pgheap for imx6

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-03-01 12:18:47 +08:00
Xiang Xiao
da954956e7 Simplify DEFAULT_SMALL usage in Kconfig 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-03-01 03:15:01 +08:00
chao.an
0961f12e28 arm/phy62xx: remove unused private header 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-03-01 00:33:58 +08:00
Masayuki Ishikawa
56e0e6a5ec arch: imx6: Remove sem_t from imx_serial.c 
Summary:
- I noticed that when exiting getprime, DEBUGASSERT happens in
  nxsem_wait()
- Finally, I found that up_putc() uses nxsem_wait()
- This commit fixes this issue by removing the semaphore.
- Also, up_putc() now calls imx_lowputc()

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-02-28 16:09:01 +08:00
Masayuki Ishikawa
a75d905760 arch: imx6: Refactor imx_lowputc() 
Summary:
- Remove '\n' -> '\r\n' conversion
- Remove waiting for FIFO empty after sending a character
- Remove CONFIG_DEBUG_FEATURES

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-02-28 16:09:01 +08:00
Xiang Xiao
872c570343 arch: Align the implementation of stack related functions 
arm: Avoid call k[u]mm_memalign to save the code size
ceva: Correct stack_base_ptr usage(top of stack v.s. bottom of stack)
mips: Correct the stack alignment in up_use_stack
misoc: Correct the stack alignment in up_use_stack
or1k: Correct the stack alignment in up_use_stack

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-28 15:05:41 +08:00
Xiang Xiao
3bf416e8b8 arch: Move STACK_ALIGNMENT definition to up_internal.h 
to avoid the same macro duplicate to many place

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-28 15:05:41 +08:00
Xiang Xiao
44bd3212d4 arch: Remove SYS_RESERVED from Kconfg 
let's arch define the correct value instead

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-27 22:54:13 +08:00
Xiang Xiao
087b9e5ff3 arch: Move the content from svcall.h to syscall.h 
and remove svcall.h

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-27 22:54:13 +08:00
Xiang Xiao
0c7517e579 arch: Remove the duplicated syscall.h in each arch 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-27 22:54:13 +08:00
chao.an
b57e0b6118 arm/armv7-a/r: check ARMV7A_DECODEFIQ on dataabort 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-27 17:25:22 +09:00
chao.an
c369e47107 arm/armv7-a/r: handle swi on interrupt stack 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-27 17:25:22 +09:00
lp.xiao
fac10b6ebd stm32f103re has a dac module.but the pinmap file has no corresponding definition 2022-02-27 14:39:17 +08:00
Xiang Xiao
b95022f8de arm/armv7-a: Remove CONFIG_SMP guard from arm_scu.c 
since ACTLR.SMP need enable to make cache work on Cortex A7:
https://developer.arm.com/documentation/ddi0464/f/CHDBIEIF

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-26 14:15:30 +09:00
Masayuki Ishikawa
de95a8550f arch, board: Add thumb support to i.MX6 
Summary:
- This commit adds thumb support to i.MX6
- Also, applies the same coding style to arch_elf.c

Impact:
- i.MX6 only

Testing:
- Tested with sabre-6quad:smp (QEMU, Dev board)
- Tested with sabre-6quad:netnsh (QEMU)
- Tested with sabre-6quad:netknsh (QEMU, not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-02-25 10:51:12 +08:00
Xiang Xiao
25213c42a5 arch/arm: Remove the empty spinlock.h file 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-25 09:18:53 +09:00
Anton Potapov
9603b8f67c Add DAC2 configuration for stm32f405. 2022-02-24 12:09:41 -05:00
Xiang Xiao
d7fe0127b0 Replece clock_gettime(CLOCK_REALTIME) with clock_systime_timespec if suitable 
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-24 01:06:36 +08:00
Xiang Xiao
43f57240e0 Replece clock_gettime(CLOCK_MONOTONIC) with clock_systime_timespec 
it's better to call the kernrel api insteaad user space api in kernel

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-24 01:06:36 +08:00
chao.an
13889ba868 arch/arm: unify some duplicate code to common layer 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-23 21:35:55 +08:00
chao.an
6cc0aaf5b9 arch/arm: unify switch context from software interrupt 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-23 15:04:29 +09:00
chao.an
db3a40ac25 arch/armv7-r: unify switch context from software interrupt 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-23 15:04:29 +09:00
chao.an
61cd9dfca1 arch/armv7-a: unify switch context from software interrupt 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-23 15:04:29 +09:00
Gregory Nutt
1ded8bbabb Garbage configuration setting in EFM32 code 
arch/arm/src/efm32/efm32_start.c:

      /* For the case of the separate user-/kernel-space build, perform whatever
       * platform specific initialization of the user memory is required.
      * Normally this just means initializing the user space .data and .bss
       * segments.
       */

    #ifdef CONFIG_NUTTX_KERNEL
      efm32_userspace();
      showprogress('E');
    #endif

But there is no CONFIG_NUTTX_KERNEL configuration setting.  Comparing this to other architectures it is clear this should be

    #ifdef CONFIG_BUILD_PROTECTED
 2022-02-23 03:40:44 +08:00
Xiang Xiao
f1ed349dd9 sched/clock: Remove CLOCK_MONOTONIC option from Kconfig 
here is the reason:
1.clock_systime_timespec(core function) always exist regardless the setting
2.CLOCK_MONOTONIC is a foundamental clock type required by many places

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-23 01:21:26 +08:00
chao.an
0aa0022b12 arch/armv7-a: replace SYS_signal_handler_return hardcode 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-22 17:59:02 +08:00
chao.an
e0fabbfdd6 arch/arm: replace SYS_syscall_return hardcode from syscall 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-22 17:59:02 +08:00
Xiang Xiao
163fe4ff0b boards: Replace CONFIG_CYGWIN_WINTOOL with CONVERT_PATH 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-20 21:15:36 +01:00
Xiang Xiao
1d1bdd85a3 Remove the double blank line from source files 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-20 20:10:14 +01:00
Oki Minabe
e9a94a003d old arm: add BUILD_KERNEL code in arm/arm_vectors.S 2022-02-20 21:03:54 +09:00
Oki Minabe
19e5c8f6d3 armv7-a/r: fix SVC's sp restore in arm_vectors.S 2022-02-20 18:39:30 +08:00
Xiang Xiao
d29f3bd21c arm/rtl8720c: Remove the unused Toolchain.defs 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-20 04:15:34 +01:00
lp.xiao
bc12260540 dp83848c ethernet phy interrupt support 2022-02-17 08:00:53 +01:00
Alan Rosenthal
8defb843aa Remove duplicate linker script definitions 
## Summary
A lot of linker scripts were listed twice, once for unix, once for windows.

This PR cleans up the logic so they're only listed once.

 ## Impact
Any opportunity to use a single source of truth and reduce lines of code is a win!

 ## Testing
CI will test all build
 2022-02-17 02:55:25 +08:00
Oki Minabe
68a305438b fix armv7-a gtm.h GTM_COMP1 and GTM_AUTO defines. 2022-02-16 18:50:42 +01:00
Oki Minabe
c1ea37742b fix arm FPSCR typos in comments. 2022-02-17 01:08:11 +08:00
Simon Filgis
cf008c94cc arch/arm/samv7: fix peripheral id shift during transmit xdma configuration 2022-02-16 17:16:53 +01:00
Masayuki Ishikawa
b60b6120de arch: armv7-a: Fix arm_syscall for SYS_pthread_start 
Summary:
- I noticed that pthread always crashes when started
  if CONFIG_BUILD_KERNEL=y
- This commit fixes this issue

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-02-16 13:06:25 +01:00
Petro Karashchenko
41c95da594 register_driver: fix driver modes accross the code 
State of problem:
 - Some drivers that do not support write operations (does not
   have write handler or ioctl do not perform any write actions)
   are registered with write permissions
 - Some drivers that do not support read operation (does not
   have read handler or ioctl do not perform any read actions)
   are registered with read permissions
 - Some drivers are registered with execute permissions

Solution:
 - Iterate code where register_driver() is used and change 'mode'
   parameter to reflect the actual read/write operations executed
   by a driver
 - Remove execute permissions from 'mode' parameter

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-02-16 16:15:29 +08:00
Masayuki Ishikawa
34cf6949ac arch: armv7-a: Add debug messages for addrenv 
Summary:
- This commit adds debug messages for addrenv

Impact:
- None

Testing:
- Tested with sabre-6quad:netknsh (not merged yet)

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-02-15 17:22:52 +08:00
Masayuki Ishikawa
e7cb1b4fb1 arch: rt8920c: Move -fno-common option to ARCHCFLAGS/ARCHCXXFLAGS 
Summary:
- Apply the same style as sabre-6quad

Impact:
- None

Testing:
- Build only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-02-15 16:27:53 +08:00
fenghang
555d25633a add phyplus_rel_1.4 
update source for phyplus driver rel_1.4

update source  for phyplus driver rel 1.4

update source for phyplus driver 1.4

update phy6222 config files
 2022-02-15 10:21:10 +08:00
Xiang Xiao
4207882cdc arm/armv8-m: Handle the special irq correctly in up_secure_irq 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-15 09:45:34 +09:00
David Sidrane
1ca952243c stm32h7:flash can not use usleep 
commit 328374f4658d11655f268f968f4c6c7a3942f320

   changed the wait to use usleep. This killed the
   write performace from the published values in the
   datasheet of ~100 us to 2 mS per 256 bits. On
   a 1000 per tick config. It can be 10 X worse
   on the default 100 per tick config.

   This changes uses up_udelay.
 2022-02-15 02:09:04 +08:00
David Sidrane
8659a31c9d stm32h7:flash Fix lock violations 2022-02-15 02:09:04 +08:00
David Sidrane
8ca4cf49b1 stm32h7:Fix build for all config {R|T}XDMA states 2022-02-14 18:43:30 +01:00
Xiang Xiao
17a7d612df arch: Replace nx_vsyslog with vsyslog 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-14 09:41:45 -03:00
chao.an
4be416a2a8 arm/backtrace: fix the compile warning 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-14 16:29:38 +08:00
raiden00pl
00917bfe9d stm32/fdcan: add CAN FD frames support 2022-02-14 10:42:01 +08:00
raiden00pl
dd8408a973 stm32/fdcan: use array indexes when accessing RX/TX FIFO 2022-02-14 10:42:01 +08:00
Michael Jung
70dae3bb3b Add arm_tcbinfo.c to stm32u5's common C sources 
And re-order the list of common C sources alphabetically.

Signed-off-by: Michael Jung <mijung@gmx.net>
 2022-02-13 16:32:35 +08:00
Michael Jung
5c1c939cdc stm32u5: Architecture Support for STM32U5 
Architecture support for STMicroelectronics STMU585xx MCUs.  This is
based on corresponding code for STM32L5, but has been considerably
adjusted.  Tested with a B-U585I-IOT02A board and a simple NSH
configuration, but only running NuttX in the non-secure world with
TrustedFirmware-M.

Signed-off-by: Michael Jung <mijung@gmx.net>
 2022-02-13 16:32:35 +08:00
Michal Lenc
56b3fc0ef9 arch/arm/src/samv7: added support for PWM driver 
This commit adds initial support for PWM driver to SAM MCU series.
Only general PWM on PWMH output is currently supported, complementary
output on PWML is not allowed. The current state of the driver also does
not support external triggering of other perihperals.

Multichannel option is supported. The functionality of the driver was
tested on an example pwm application and with a real time control system.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2022-02-13 03:20:07 +08:00
Huang Qi
95b0c85f58 arch: Add xxx_tcbinfo.c to SoC level Make.defs 
Fix build break with CONFIG_DEBUG_TCBINFO enabled.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-12 21:07:35 +09:00
zhuyanlin
3ab65f9b08 armv7-a/r: use flush/clean_all if size large than cache size 
For cache flush/clean performance

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-09 18:16:31 +01:00
zhuyanlin
4eba2f3527 armv7-a/r:cache: add cp15_cache_size function 
Add cp15_cache_size function for armv7-a/r

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-09 18:16:31 +01:00
Huang Qi
c0a0de97ce Revert "libc: Call pthread_exit in user-space by up_pthread_exit" 
This reverts commit f4a0b7aedd.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
 2022-02-09 21:21:43 +08:00
Alin Jerpelea
7a674b6287 Makefiles: change license to Apache 
Make files are recipes based on contributions from from Gregory Nutt

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2022-02-09 19:58:52 +08:00
zhuyanlin
cc8ab23550 armv7-r/a: fix a4 register use in xxx_invalidate/flush/clean_all.S 
Use sub loop instead of add loop

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-02-08 19:39:43 +09:00
SPRESENSE
8de07b2ae8 boards: cxd56xx: audio: Support I2S input 
Enable the driver setting of I2S input.
 2022-02-08 10:47:03 +01:00
raiden00pl
bc178344a9 net/can: add an option to control CAN EXTID support 2022-02-06 17:09:11 +08:00
raiden00pl
341bbe38d5 arch/stm32: add FDCAN SocketCAN support 2022-02-06 17:09:11 +08:00
Petro Karashchenko
e545c440f4 arch/arm/samv7/sam_progmem: insert DMB instruction into data write loop 
This change fix the regression that was introduced with
https://github.com/apache/incubator-nuttx/pull/4904

In case if D-Cache in configured in Write-Through mode there is
Cortex-M7 erata 1313001 that describes a situation when linefill
buffer or cache contains stale data. Even if progmem write loop
does not fully matches the description there is a possibility
to program stale data if there is no DMB instruction after each
write operation to progmem latch buffer.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-02-05 03:14:07 +08:00
Petro Karashchenko
47a09ed255 arch/arm/samv7: add arm_systemreset.c to CMN_CSRCS 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-02-04 16:40:50 +08:00
chao.an
ed4f852073 arch/arm: correct the sched_lock/spin_lock handling 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-03 11:09:18 -03:00
chao.an
d59931159a arch/arm: fix leaving from critical section 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-02-02 21:45:13 +08:00
Xiang Xiao
4c167b0729 Correct the code alignment 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-02-01 21:22:21 -03:00
Petro Karashchenko
601a0e8a32 arch/arm/samv7: fix leaving from critical section in HSMCI callback 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-31 16:56:52 -03:00
Xiang Xiao
2c3020ddaf arch/Toolchain.defs: Replace --print-file-name=libgcc.a with --print-libgcc-file-name 
to more compatable with clang: https://reviews.llvm.org/D25338

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-31 09:46:04 +01:00
Xiang Xiao
e0b62bf677 arch/Toolchain.defs: Don't expand EXTRA_LIBS immediately 
since board's Make.defs may overwrite ARCHCPUFLAGS

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-30 11:04:35 +09:00
David Sidrane
0f1342f36b stm32:Add OTG ID GPIO disable 2022-01-30 01:50:37 +08:00
David Sidrane
99083b8dd1 stm32{f|h}7:Fixed typo in Kconfig help 2022-01-30 01:49:57 +08:00
chao.an
7d8c2c1ad6 cortex-m/doirq: do not update the CURRENT_REGS on nested interrupt handling 
current implementation incorrectly update CURRENT_REGS to interrupt context if
trigger nested interrupt, (e.g, hard fault occurs during interrupt handling)
this would ambiguous for programs using CURRENT_REGS, this patch will prohibit
the update of CURRENT_REGS on nested interrupt handling

Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-01-29 01:04:00 +08:00
Xiang Xiao
1c2c0e4707 arch/Toolchain.defs: Simplify the builtin library addition for EXTRA_LIBS 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-28 12:02:38 +01:00
Petro Karashchenko
0ffffe19b1 typo: change evernt to event in comments 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-27 09:57:31 -03:00
Xiang Xiao
f903a55102 sched/tcbinfo: Fix the compile warning 
Update tcbinfo struct

armv8-m/arm_tcbinfo.c:109:3: warning: excess elements in struct initializer
  109 |   TCB_REG_OFF(REG_S31),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:109:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:110:3: warning: excess elements in struct initializer
  110 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:110:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:111:3: warning: excess elements in struct initializer
  111 |   TCB_REG_OFF(REG_FPSCR),
      |   ^~~~~~~~~~~
armv8-m/arm_tcbinfo.c:111:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:112:3: warning: excess elements in struct initializer
  112 |   0,
      |   ^
armv8-m/arm_tcbinfo.c:112:3: note: (near initialization for 'g_tcbinfo')
armv8-m/arm_tcbinfo.c:37:1: warning: missing braces around initializer [-Wmissing-braces]
   37 | {

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-27 17:36:27 +08:00
zhuyanlin
644c2be3aa armv7-a/r:cache: implemention clean&flush_dcache_all 
For armv7-a/r cache:
And clean_dcache_all, flush_dcache_all

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-27 15:15:28 +08:00
zhuyanlin
1b08f607be arm/xtensa:cache: flush/clean dcache all if size large than cache size 
For performance, if size large than cache size, use xxx_all instead

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2022-01-27 15:15:28 +08:00
zhuyanlin
4d5c2586a9 armv7-a/r:cp15_invalidate_dcache_all: fix Sets mask error. 
As NumSets field is bits 13-27, use 0x7fff instead.
And add way to get from CCSIDR.
 2022-01-27 15:13:08 +08:00
Petro Karashchenko
48211f90d3 ci: select ARMV7A_TOOLCHAIN_GNU_EABIL for ARMv7-A based builds 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-25 20:24:28 +08:00
Masayuki Ishikawa
7b1cf2dfac arch: arm: Fix make export for armv7-a SoCs 
Summary:
- I noticed that make export does not work with swama5d4-ek:knsh
- This commit fixes this issue.
- NOTE: apps/Makefile also needs to be updated.

Impact:
- CONFIG_BUILD_KERNEL=y only

Testing:
- Build (make and make export) with sama5d4-ek:knsh

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2022-01-25 11:05:22 +08:00
Norman Rasmussen
da5659138b Fix regression where used code was marked as unused 
Commit 5d1a444812 replaced __attribute__
((unused)) with unused_code but two instances of __attribute__ ((used))
were also incorrectly replaced. Add used_code/used_data and used them
instead.
 2022-01-23 14:57:19 +08:00
raiden00pl
4c2dd3924a include/nuttx/can.h: rename CAN_ERR_CTRL to CAN_ERR_CRTL for compatibility with libcanutils 2022-01-23 01:34:34 +08:00
Petro Karashchenko
6c27f3c19d toolchain: add libm to EXTRA_LIBS only if it is provided by the compiler 
Some toolchains may be built without libm support, but using
such toochain should not generate any errors in case if math
functions are not used in the program

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-22 15:36:29 +08:00
Xu Xingliang
021363f1db driver/mmcsd: add option to limit block count in multiple-block transfer mode. 
Signed-off-by: Xu Xingliang <xuxingliang@xiaomi.com>
 2022-01-22 14:59:26 +08:00
zouboan
0342272e5a up_progmem_erasesize for stm32f20xxf40xx_flash.c 2022-01-21 14:57:32 +08:00
Xiang Xiao
2935751bfd Fix error: implicit declaration of function 'up_cpu_index' 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 23:21:21 +08:00
Xiang Xiao
77792a1598 sched: Define CONFIG_SMP_NCPUS to 1 in no SMP case 
to simplify the SMP related code logic

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-20 23:21:21 +08:00
Petro Karashchenko
08043fb5bc net: unify FAR keyword usage for all net buffer memory mapped buffers 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-20 01:42:56 +08:00
Petro Karashchenko
767cf282c7 boards/arm/samv7: move HSMCI interface to common 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-20 01:24:14 +08:00
Daniel Agar
12c8a9626c stm32f7 serial fix PM_CONFIG build 2022-01-20 01:08:06 +08:00
Petro Karashchenko
a6147109b1 arch/arm/src/armv6-m: fix typo 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-19 15:32:58 +01:00
Xiang Xiao
8bcdefafc9 board: Remove -fno-strength-reduce 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-19 00:14:03 +01:00
Petro Karashchenko
9551de7115 net: use HTONS, NTOHS, HTONL, NTOHL macro in kernel code 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-18 10:59:47 +01:00
raiden00pl
e140ba1a21 arch/stm32: fdcan cosmetics 2022-01-17 09:36:00 -03:00
raiden00pl
c450dea6e5 stm32: add FDCAN support 
based on PR #2987
 2022-01-17 09:36:00 -03:00
Petro Karashchenko
4f98ac4879 arch/arm/samv7: implement quadrature encoder driver 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-17 09:35:12 -03:00
Petro Karashchenko
8d3bf05fd2 include: fix double include pre-processor guards 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-16 11:11:14 -03:00
chao.an
c27839f98e arm/xtensa: save the running registers to xcp context 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-01-15 02:20:01 +08:00
Jari van Ewijk
3aed0aa641 S32K1XX: implement uniqueid 2022-01-13 15:34:47 -08:00
Jari van Ewijk
0fc613f0b3 S32K1XX Reset Cause PROCFS: Add Kconfig option and cleanup 2022-01-13 01:29:42 +08:00
Xiang Xiao
1b77ae88ef fs/procfs: Remove the unnecessary strcmp 
since the procfs already make the same check for us

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2022-01-12 07:19:40 +01:00
Petro Karashchenko
a743fed63d file_operations: get back C89 compatible initializer 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-11 02:14:00 +08:00
Petro Karashchenko
1fd51ccbe2 arch/arm/samv7: rework SAMv7 timer counter implementation 
There are two issues that are addressed with this change:
 - According to SAM E70/S70/V70/V71 Family datasheet the
   timer counter channels are 16-bit so timer counter
   value should be changed from uint32_t to uint16_t
 - The interrupt handling for timer counter channels can
   be simplified

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-09 17:43:31 +08:00
Petro Karashchenko
e7f9c7af21 typos: fix typos in Kconfig files 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-08 06:46:26 -03:00
chao.an
8c35d31808 Kconfig: Remove CONFIG_ prefix from config definition 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2022-01-07 13:16:18 +08:00
raiden00pl
6fe95d8314 stm32: add SocketCAN support, based on stm32_can.c 2022-01-05 06:16:41 -08:00
Zeng Zhaoxiu
fb43fd73ed signal: signal handler may cause task's state error 
For example, task is blocked by nxsem_wait(sem1), use nxsem_wait(sem2)
in signal handler, and take sem2 successfully, after exit from signal
handler to task, nxsem_wait(sem1) returns OK, but the correct result
should be -EINTR.

Signed-off-by: Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com>
 2022-01-05 21:36:44 +09:00
raiden00pl
5b9b3814f8 stm32: add CAN error support 2022-01-05 18:33:06 +08:00
Petro Karashchenko
4b190fbce1 arch/arm/samv7: correct number on interrupts 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-03 22:10:22 +08:00
Petro Karashchenko
6c2b40f98a typos: fix typos in many files 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-03 22:10:07 +08:00
Petro Karashchenko
c7d3a674fd drivers/sensors/as5048b: fix lower half init issue 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-03 11:38:44 +08:00
Petro Karashchenko
d23ad9b9b0 userspace: fix typos in comments 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2022-01-02 20:50:30 +01:00
chao.an
736add0fe8 arch/backtrace: correct the skip counter 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-30 16:57:40 +08:00
Xiang Xiao
b92c90ee81 arch/arm: Fix rebase error in arm_backtrace_thumb.c 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-29 20:42:05 +08:00
chao.an
7ed0b97414 make/allsyms: skip the unnecessary link operation 
For incremental compilation, skip the stage 1 dummy link
operation if nuttx elf has been generated

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-28 23:47:10 -06:00
Xiang Xiao
dd942f0b04 sched/backtrace: Dump the complete stack regardless the depth 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-29 12:09:54 +08:00
chao.an
cf2dfa8985 arch/arm/assert: move the arm_assert to common code 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-28 05:09:30 -06:00
chao.an
579738c8fa arch/arm: move the backtrace implement to common code 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-28 03:02:01 -06:00
chao.an
a42aa8415d compile/flags: add FRAME_POINTER into Toolchain.defs 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-27 22:31:27 -06:00
chao.an
8eb999ff03 arch/arm: select ARM_THUMB by default for Cortex-M 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-27 22:30:53 -06:00
Petro Karashchenko
3ccb657dc2 nuttx: remove space befone newline in logs 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-27 21:01:19 -06:00
chao.an
6069433d2d arch/arm/cortex-a/r: dump all registers with alias 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-23 06:54:32 -06:00
David Sidrane
74e692b3c1 stm32f7:sdmmc invalidate before DMA to avoid eviction overwrite 
For FAT the same buffer is used for read and writes, there
  is a possibility a cache line is dirty. But the fs is
  not dirty and will not write the sector to disk. This can
  be seen  https://github.com/PX4/NuttX/pull/175

  When the system is busy that cache line can be evicted after the
  RX DMA has completed and overwrite the data in memory. The solution
  is to invalidate before the DMA to prevent an evection causing an
  overwite, and after the DMA it to insure coherency.
 2021-12-22 20:44:04 -06:00
chao.an
a0b61bbf6f arm/cortex-a/r: enhance the task dump 
add irq stack information
add cpu loading

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-22 11:46:02 -03:00
chao.an
2737701996 cortex-m/hardfault: add secure-fault handler 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-21 07:08:13 -06:00
Juha Niskanen
422ceec99b Fix typos in comments and Kconfig files 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-12-21 03:26:16 -06:00
Simon Filgis
6cc48ff6ff arch/arm/samv7: initial support for LIN bus communication 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 18:23:05 -03:00
Petro Karashchenko
3e76c3266e assert: unify stack and register dump across platforms 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-20 00:02:12 -03:00
David Sidrane
e269b5fa28 Revert "stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. When it was in slow speed mode (by default), the output SDMMC_CK clock rise and fall times were about 13 ns each, that were very slow and prevented some SDIO devices from working." 
This reverts commit 0aecfe8691.
 2021-12-19 01:40:35 -06:00
raiden00pl
87a8b1bed9 nrf52/Kconfig: NRF52_SDC_LE_CODED_PHY not available for nrf52832 2021-12-18 12:27:59 -06:00
raiden00pl
f3fdd5a019 arch/arm/src/nrf52/Kconfig: select IRQPRIO for SoftDevice 2021-12-18 09:13:36 -06:00
raiden00pl
a6c64795f4 arch/arm/src/nrf52/nrf52_sdc.c: raise error if BT device not selected 2021-12-18 09:13:36 -06:00
raiden00pl
cf2dae8d79 arch/arm/src/nrf52/nrf52_sdc.c: nxstyle fixes 2021-12-17 12:35:17 -06:00
raiden00pl
af143c96fc arch/arm/src/nrf52/nrf52_sdc.c: public device address and static device address support 2021-12-17 12:35:17 -06:00
raiden00pl
c7f6ac63b0 arch/arm/src/nrf52/nrf52_sdc.c: add option to register UART H4 device 2021-12-17 12:35:17 -06:00
raiden00pl
23ef3ea64c arch/arm/src/nrf52/nrf52_sdc.c: remove nedless new lines 2021-12-17 12:35:17 -06:00
raiden00pl
26951f5018 arch/arm/src/nrf52/nrf52_sdc.c: print HCI opcode as hex 2021-12-17 12:35:17 -06:00
raiden00pl
07c9204fd6 arch/arm/src/nrf52/nrf52_sdc.c: fix status byte offset 2021-12-17 12:35:17 -06:00
raiden00pl
ab66800e13 arch/arm/src/nrf52/Kconfig: fix typos 2021-12-17 12:35:17 -06:00
raiden00pl
ba6e8696b2 arch/arm/src/nrf52/hardware/nrf52_ficr.h: add device address types 2021-12-17 12:35:17 -06:00
raiden00pl
07d295b8db add 5-Clause Nordic License barrier for Nordic SoftDevice Controller 2021-12-17 11:22:39 -06:00
Gerson Fernando Budke
2dd5578d50 arch/arm/src/samv7/Kconfig: Define mem sizes 
Current samv7 platform does not define SoC memories sizes. This define
both internal flash and sram memories sizes and update all defconfig
files.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
 2021-12-16 06:56:42 -03:00
Alexander Lunev
0aecfe8691 stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. 
When it was in slow speed mode (by default), the output SDMMC_CK clock rise and
fall times were about 13 ns each, that were very slow and
prevented some SDIO devices from working.
 2021-12-16 01:28:05 -06:00
chao.an
b11833cbba arch/assert: flush the syslog before stack dump 
flush the syslog before stack dump to avoid buffer overwrite

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-15 12:00:35 -06:00
Petro Karashchenko
51a2db6ffc Kconfig: improve uniformity 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-14 07:32:48 -06:00
Petro Karashchenko
af614ac77d tls: restore C89 compatibility for TLS 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-12-13 21:14:53 -06:00
chao.an
c2fd66bfab arch/arm/risc-v/xtensa: add support of all symbols for debugging 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-13 08:31:13 -06:00
chao.an
89e2f00dad arch/assert: fix the stack dump overflow 
[ EMERG] kasan_report: kasan detected a read access error, address at 0x3c24fca8, size is 4
[ EMERG] up_assert: Assertion failed at file:kasan/kasan.c line: 104 task: init
[ EMERG] backtrace|10:  0x2c334666 0x2c35f0d6 0x2c359ef6 0x2c35f830 0x2c360ed4 0x2c3615c0 0x2c324e0c 0x2c30a168
[ EMERG] up_registerdump: R0: ffffffff R1: 00000004 R2: ffffffff R3: ffffffff
[ EMERG] up_registerdump: R4: 3c20d4f0 R5: 2c35acd5 R6: 00000000 FP: 3c24fae8
[ EMERG] up_registerdump: R8: 3c20d504 SB: ffffffff SL: 2c413e7c R11: 2c411eb8
[ EMERG] up_registerdump: IP: 00000002 SP: 3c24fae8 LR: 00000003 PC: 2c35f0d6
[ EMERG] up_registerdump: xPSR: 61010000 BASEPRI: 000000e0 CONTROL: 00000004

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-13 01:43:18 -06:00
chao.an
0b7b8d274f arm/cortex-m: enhance the crash dump 
1. add irq stack information to list
2. add cpu loading into list

before:

Idle Task: PID=0 PRI=0 Stack Used=512 of 3048
hpwork: PID=1 PRI=224 Stack Used=304 of 2016
lpwork: PID=2 PRI=100 Stack Used=304 of 2016
rptun: PID=4 PRI=224 Stack Used=856 of 2008

after:

[ EMERG] [ap] up_showtasks:    PID    PRI      USED     STACK   FILLED       CPU   COMMAND
[ EMERG] [ap] up_showtasks:   ----   ----       928      2048    45.3%      ----   irq
[ EMERG] [ap] up_dump_task:      0      0       512      3048    16.7%     99.4%   Idle Task
[ EMERG] [ap] up_dump_task:      1    224       304      2016    15.0%      0.0%   hpwork
[ EMERG] [ap] up_dump_task:      2    100       304      2016    15.0%      0.0%   lpwork
[ EMERG] [ap] up_dump_task:      4    224       856      2008    42.6%      0.0%   rptun

Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-12 21:40:29 -06:00
Matheus Castello
294694bb2f arch: arm: select LIBC_ARCH_ATOMIC when config ARCH_CHIP_RP2040 
Use the common atomic operations when needed.

Signed-off-by: Matheus Castello <matheus@castello.eng.br>
 2021-12-11 11:32:17 -06:00
Juha Niskanen
a35d205f3b arch/arm/src/stm32l4/stm32l4_pwm.c: fix printf format 
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2021-12-10 12:30:26 -06:00
Daniel Agar
efc949bceb arch/arm/src/stm32/Kconfig STM32_STM32F412 add SPI2 & SPI3 2021-12-09 21:30:41 -06:00
chao.an
3d75c25737 cortex-m/hardfault: enhance the dump information of mem/hard-fault 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 11:42:21 -06:00
chao.an
66e604b40e cortex-m/hardfault: add usage-fault handler 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 11:42:21 -06:00
chao.an
2f449245cc cortex-m/hardfault: add bus-fault handler 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 11:42:21 -06:00
chao.an
99fa58c871 arm/cortex-m23: armv8-m baseline do not support mem-fault 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 05:36:00 -06:00
chao.an
3e812dd88c cortex-m/fault: add CFSR(Configurable Fault Status Register) Definitions 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 04:30:06 -06:00
Xiang Xiao
6357523892 arch: Add _wchar_t typedef like other basic types 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-09 16:57:23 +09:00
chao.an
9b502dca05 arm/backtrace: disable the sanitize address check 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 01:05:46 -06:00
chao.an
7a61588b00 cortex-m/backtrace: remove the push process to simplify backtrace 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 01:05:46 -06:00
chao.an
437c81f8d0 cortex-m/assert: dump all registers with alias 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-09 00:16:04 -06:00
Michal Lenc
ae57492189 samv7: enable MCAN driver support for both rev A and rev B 
This commit enables the MCAN driver to function with both rev A and rev B
version of the chip. The version of the chip is selected automtically from
SAM_CHIPID_CIDR register so there is no need to predefined it in the
configuration.

The functonality was tested on rev B version of the chip. The rev A was
not tested since I do not have the functional board but the code remains
the same as in the previous NuttX version so it should not cause any
additional troubles.

The code is co-authored by Miloš Pokorný who wrote the initial transition
to rev B of the chip.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
Co-authored-by: Miloš Pokorný <milos.pokorny@seznam.cz>
 2021-12-07 23:36:11 -06:00
Huang Qi
58e0781e2e arch/arm: Implement TLS support 
Signed-off-by: Huang Qi <no1wudi@qq.com>
 2021-12-07 23:31:41 -06:00
Masayuki Ishikawa
bec9058b4c arch: lc823450: Replace the critical section with spinlock in lc823450_serial.c 
Summary:
- This commit replaces the critical section with spinlock
- The logic is the same as cxd56_serial.c

Impact:
- None

Testing:
- Tested with lc823450-xgevk:bt

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2021-12-07 23:28:54 -06:00
fenghang
c39ef4420e 1.phyplus update files to accord with the requirement of chcekpatch.sh 
2.fix some files to fix compile warning

3.remove blueteeth header files, which are not used in nuttx core.

4.fix configs and add lost files

5.update defconfig, remove useless items

6.fix compile warning for nuttx phyplus

7.delete useless: ble, h4, zblue defconfig files form phyplus configure folder

8.fix file format check error on phyplus source code

9.fix phyplus kconfig param error

10.update configure file for nuttx
 2021-12-07 01:37:29 -06:00
fenghang
073c9880a3 phyplus first submit 2021-12-07 01:37:29 -06:00
chao.an
437a30d117 arch/tcbinfo: fix build break if task name disabled 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-12-06 00:47:58 -06:00
Xiang Xiao
a0990ee416 arch: Remove the duplicated up_tls_info implementation 
Define up_tls_info in arch/arch.h directly if the general one isn't suitable

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-05 20:59:53 -06:00
Xiang Xiao
19e5ee6ce0 arch: Remove FILE dump code from _up_dumponexit 
since the kernel build can't access the userspace memory
inside other process directly

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-06 11:23:58 +09:00
Xiang Xiao
b65c7c26cf arch: Dump task name through tcb_s::name instead of argv[0] 
since argv is defined in task_tcb_s not tcb_s

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-12-01 16:04:15 +01:00
Gerson Fernando Budke
c3307fce6b arch/arm/Kconfig: Add ARCH_HAVE_PROGMEM config 
The Atmel samv7 implements progmem functionality. However, there is
missing ARCH_HAVE_PROGMEM Kconfig symbol. This add missing symbol.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
 2021-11-29 21:31:08 -06:00
Petro Karashchenko
31809724e1 boards/same70-xplained: disable systick before loading MCUboot application 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-28 20:33:53 -06:00
Petro Karashchenko
fae27cc945 arch/samv7: fix unaligned address write for progmem interface 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-28 11:04:28 -06:00
Michal Lenc
ce53ea5da6 arch/arm/src/samv7: add DMA and TC trigger support to AFEC driver 
This commit adds DMA and TC support to SAMV7 AFEC driver. The AFEC (ADC)
can now be triggered by Timer/counter at chosen frewuency and samples can
be transfered via DMA with configurable number of samples. Timer/counter
trigger is now set as a default option with the possibility to change it
to software generated trigger.

DMA is inspired by SAMA5 driver and also uses ping pong buffers.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-11-27 06:17:45 -06:00
Michal Lenc
6f2e23ad0c arch/arm/src/samv7/sam_tc.c: fix compile warnings and errors 
Just a minor change fixing some compile warnings and errros, does not have
any impact on functionality.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-11-27 06:17:45 -06:00
Petro Karashchenko
0d9425676d arch/arm/src/samv7: add flash progmem erasestate ioctl support 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-26 14:55:34 -03:00
Petro Karashchenko
134b2e6ec9 arch/arm/include/samv7: fix typo in samv7 irq header files 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-26 14:55:34 -03:00
Petro Karashchenko
dd647d200e arch/samv7/sam_progmem: fix page size flash writing 
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
 2021-11-26 08:47:08 -06:00
zhuyanlin
1b3005accf arch:cache_invalidate: fix unalign cacheline invalidate 
Only invalidate may corrupt data in unalign start and end.
Use writeback and invalidate instead.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-24 22:48:13 -06:00
zhuyanlin
4db5016d83 arch:hostfs: add cache coherence config for semihosting option 
N/A

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-24 22:48:13 -06:00
David Sidrane
ad7e36d83f stm32f7:sdmmc defer invalidate until after DMA completion 
The FAT was not coherent. Resulting in a write failed
   with errno:28 No space left on device.

   It is unclear how the memory is acesses prior to the DMA
   completion. But this restructuring ensures the data
   is coherent.

   This issue was not detected on the stm32h7
 2021-11-24 20:38:23 -06:00
chao.an
7cbb8da692 binfmt/elf: add bare metal coredump support 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-11-23 20:48:00 -06:00
chao.an
4c76c356ef arch/arm: add more arch elf define 
Signed-off-by: chao.an <anchao@xiaomi.com>
 2021-11-23 20:34:56 +09:00
Xiang Xiao
a29ee19af4 driver/motor: Remove the unnecessary critical section operation 
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
Signed-off-by: Jiuzhu Dong <dongjiuzhu1@xiaomi.com>
 2021-11-18 19:27:07 -06:00
Xiang Xiao
a799835ec6 arch/arm: Remove EXPERIMENTAL from ARCH_TRUSTZONE_XXX 
since it work on the product device

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-11-17 08:59:14 -03:00
Andres Sanchez
064f6c8c55 add MTDIOCTL_PROGMEM_ERASESTATE support 
Signed-off-by: Andres Sanchez <tito97_sp@hotmail.com>

solve style check errors.
 2021-11-16 14:45:03 -03:00
Alin Jerpelea
6deaba896d arch: Haltian Ltd: update licenses to Apache 
Gregory Nutt has submitted the SGA
Haltian Ltd has submitted the SGA
Uros Platise has submitted the ICLA

as a result we can migrate the licenses to Apache.

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
 2021-11-15 06:49:32 -06:00
Xiang Xiao
2262ddfa6d arch: Remove fflush(stdout) from driver code 
it's wrong to call stdio function inside driver

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
 2021-11-15 00:04:12 +01:00
zhuyanlin
012bd1494c arch:debug: add struct for task aware debug. 
When enable DEBUG_TCBINFO config, a global struct will
provide, then debuggers can aware nuttx task infomation.

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
 2021-11-10 14:31:10 -03:00
Juha Niskanen
201c67acbd stm32l4 dfumode: enable for STM32L4+ chips 2021-11-10 11:18:37 -06:00
Michal Lenc
e0cef411e1 arch/arm/src/samv7: add support for AFEC (ADC) driver 
This commit adds microcontroller support for Analog Front End driver to
samv7 MCUs. Only software trigger via IOCTL is currently supported,
averaging can be set by configuration option CONFIG_SAMV7_AFECn_RES.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
 2021-11-07 21:04:56 -06:00
Yuichi Nakamura
3a0cd56623 rp2040: support I2C_RESET 2021-11-07 03:43:22 -08:00
Yuichi Nakamura
c109262a7f rp2040: add rp2040_gpio_get_function_pin() 2021-11-07 03:43:22 -08:00
raiden00pl
7b595ab73a arch/arm/stm32/stm32_qencoder: add support for Qenco index pin 2021-11-07 03:52:48 -06:00
David Sidrane
4b96c28ed4 stm32h7:Support SPI SPI_DELAY_CONTROL 2021-11-06 05:14:05 -05:00
David Sidrane
040a04241e drivers/spi:Define SPI_~CS~_DELAY_CONTROL to support other delays 2021-11-06 05:14:05 -05:00
David Sidrane
c077361a8a imxrt:usb Fix EP type allocation 2021-11-04 13:23:25 -05:00
David Sidrane
95f7f4b9e6 imxrt:usb DMA cache aligned Buffers for Endpoints 2021-11-04 13:23:25 -05:00
David Sidrane
bd2bc1e351 imxrt:usbdev Clean up cache maintainence 2021-11-04 13:23:25 -05:00
David Sidrane
c3d10ad0aa imxrt:usbdev formatting cleanup 2021-11-04 13:23:25 -05:00
David Sidrane
532635129c imxrt:usdhc add proper support for dcache (wb) 2021-11-04 13:23:25 -05:00
David Sidrane
5022244339 imxrt mpuinit:Set Data and Code Type to Normal 
Strongly-Ordered requires aligned access unless
  caching is enabled.

  Normal memory
  Accesses to normal memory region are idempotent...
  - unaligned accesses can be supported
 2021-11-04 13:23:25 -05:00
David Sidrane
34c3efcb91 imxrt mpuinit:Remove duplicate entry for ITCM (0x0) 2021-11-04 13:23:25 -05:00
David Sidrane
08d0434bad imxrt:mpu init handle dcache setting in MPU config 
With CONFIG_ARMV7M_DCACHE the cache maintenance operation
   are not present. Or if CONFIG_ARMV7M_DCACHE_WRITETHROUGH
   is on then buffering operations are no-ops.

   This change enables MPU_RASR_C and MPU_RASR_B if
   CONFIG_ARMV7M_DCACHE is only set.

   if CONFIG_ARMV7M_DCACHE_WRITETHROUGH is set then only
   MPU_RASR_C is enabled.

   N.B When caching is disalbed unaligned access may cause hard faults
   so add -mno-unaligned-access

   It is always safe to enable Buffering in FLASH to achive unaligned
   access leniency, as it is not written to.
 2021-11-04 13:23:25 -05:00
Alexander Lunev
60de445ab3 stm32h7 sdmmc: do not enable power saving configuration bit (in SD 4-bit mode) because 
the SDIO clock is not enabled when the bus goes to the idle state, that, in turn, breaks
IRQ delivering mechanism over DAT[1]/IRQ SDIO line to the host.
 2021-11-03 22:50:14 -05:00