DMA directly to user (virtual) memory won't work, as the DMA engine(s)
don't do address translations, i.e. they require a physical address.
Using kernel heap is fine as it is mapped vaddr=paddr. Also, the USB DMA
engine does not have any alignment requirements.
The hack just opens the entire SoC memory unconditionally, which is not
a good idea.
Test features can be used ad-hoc, they don't need to be supported by the
build.
and optimize the critical section usage
1.Remove the unnecessary critical section in ramlog_readnotify
2.Move the enter/leave critical section out of ramlog_pollnotify loop
3.Move the critical section of ramlog_addchar to caller
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
1.Remove RAMLOG_OVERWRITE option and related code
2.Broadcast the readability to all reader and poller
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
-The qemu wifi fucntion only supports the STA mode and the following
operations:
wapi mode wlan0 2
wapi scan wlan0
wapi psk wlan0 password 3
wapi essid wlan0 wifi_name 1
wapi show wlan0
wapi disconnect wlan0
-Eanble the virtual wifi function with the MACRO `CONFIG_DRIVERS_WIFI_SIM`.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
As pointed out in #11322 there is a hardware design issue in RISC-V that
affects RV64 relocations. The problem is with how address bits are loaded
into registers via lui / auipc and sign extension.
If the hi20 relocation value happens to have its 32-bit sign bit set, i.e.
value is 0x80000000 (but not negative! i.e. negative in 64-bit format) the
relocation will fail, as the address is erroneously sign extended:
0x00000000_80000000 becomes 0xffffffff_80000000 which is not correct.
Also, make sure the correct opcode is used with PCREL_HI20, it expects
AUIPC (not LUI). The C compiler will never emit such code but when hand-
writing assembly code this can happen.
Previously ipv6 multi-address support decided packet source
address based on its destination. This doesn't work if NuttX
device has multiple addresses within same subnet.
Instead when a packet is a response to existing connection,
the source address should be based on the destination address
used in the received packet.
Refers to https://docs.oasis-open.org/virtio/virtio/v1.2/cs01/virtio-v1.2-cs01.html#x1-2230004
A driver SHOULD negotiate VIRTIO_NET_F_MAC if the device offers it.
If the driver negotiates the VIRTIO_NET_F_MAC feature, the driver MUST
set the physical address of the NIC to mac. Otherwise, it SHOULD use a
locally-administered MAC address.
Signed-off-by: liqinhui <liqinhui@xiaomi.com>
There is a problem with the current elf loader for risc-v: when a pair of
PCREL_HI20 / LO12 relocations are encountered, it is assumed that these
will follow each other immediately, as follows:
label:
auipc a0, %pcrel_hi(symbol) // R_RISCV_PCREL_HI20
load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S
With this assumption, the hi/lo relocations are both done when a hi20
relocation entry is encountered, first to the current instruction (addr)
and to the next instruction (addr + 4).
However, this assumption is wrong. There is nothing in the elf relocation
specification[1] that mandates this. Thus, the hi/lo relocation always
needs to first fixup the hi-part, and when the lo-part is encountered, it
needs to find the corresponding hi relocation entry, via the given "label".
This necessitates (re-)visiting the relocation entries for the current
section as well as looking for "label" in the symbol table.
The NuttX elf loader does not allow such operations to be done in the
machine specific part, so this patch fixes the relocation issue by
introducing an architecture specific cache for the hi20 relocation and
symbol table entries. When a lo12 relocation is encountered, the cache
can be consulted to find the hi20 part.
[1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
otherwise NUTTX_COMMON_DIR is empty if CONFIG_ARCH_BOARD_COMMON is set from menuconfig
Co-authored-by: hartmannathan <59230071+hartmannathan@users.noreply.github.com>
The macro LOG2_CEIL is intended to be used in the pre-processor phase. If
used run-time it will generate a massive amount of extra code (~3.5K) which
is a problem, as the PMP configuration is quite often executed from a first
stage bootloader with a limited amount of code memory.
Code size differences pre- and post:
Memory region Used Size Region Size %age Used
envm: 112064 B 112384 B 99.72%
Memory region Used Size Region Size %age Used
envm: 108952 B 112384 B 96.95%
This PR adds support for the Bouffalo Lab BL808 SoC, based on T-Head C906 64-bit RISC-V Core. This will be used by the upcoming port of NuttX for PINE64 Ox64 SBC.
Most of the code was derived from NuttX for Star64 JH7110. The UART Driver was derived from BL602 NuttX. The source files are explained in the articles here: https://github.com/lupyuen/nuttx-ox64
`Kconfig`: Added ARCH_CHIP_BL808 for BL808 SoC
`include/bl808/chip.h`: BL808 Definitions
`include/bl808/irq.h`: External Interrupts
`src/bl808/chip.h`: Interrupt Stack Macro
`src/bl808/bl808_allocateheap.c`: Kernel Heap
`src/bl808/bl808_head.S`: Linux Header and Boot Code
`src/bl808/bl808_irq.c`: Configure Interrupts
`src/bl808/bl808_irq_dispatch.c`: Dispatch Interrupts
`src/bl808/bl808_memorymap.h`: Memory Map
`src/bl808/bl808_mm_init.c`, `bl808_mm_init.h`: Memory Mgmt
`src/bl808/bl808_pgalloc.c`: Page Allocator
`src/bl808/bl808_serial.c`, `bl808_serial.h`: UART Driver
`src/bl808/bl808_start.c`: Startup Code
`src/bl808/bl808_timerisr.c`: Timer Interrupt
`src/bl808/hardware/bl808_memorymap.h`: PLIC and UART Base Address
`src/bl808/hardware/bl808_plic.h`: PLIC Register Addresses
`src/bl808/hardware/bl808_uart.h`: UART Register Addresses
`src/bl808/Kconfig`: BL808 Config
`src/bl808/Make.defs`: Makefile
Commit 8a63d29c removed `devif_iob_send` from `udp_sendto_buffered`
workflow, `devif_iob_send` drops too big packet. Now we still need a
place to check the packet length, otherwise a packet larger than MTU
may be sent to the net driver.
In case of similar problem happens somewhere else, this commit also
adds a check in `netdev_upperhalf`, and count these cases into
`NETDEV_TXERRORS`.
Signed-off-by: Zhe Weng <wengzhe@xiaomi.com>
Busy waiting in w25qxxxjv_erase_sector() was without nxsig_usleep and
was causing the entire system to freeze for significant amount of time
as sector erase takes some time.
This commit adds nxsig_usleep into busy waiting to prevent system lock.
Sleep is set to sector erase time based on W25Q series datasheet.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
we can use uart to debug nuttx,like debugger:
1. read/write memory
2. Use watchpoint,breakpoint,single step.
use up_debugpoint api
3. Ctrl+c to stop, continue, or single step.
hold uart send and receive
4. register a panic event, when crash or assert/panic, we use uart to
debug.
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Currently RISC-V NuttX supports 32-bit MMU Flags inside a Page Table Entry. This PR extends the MMU Flags to 64-bit, to support T-Head C906 Core and the new RISC-V Svpbmt Extension.
T-Head C906 uses Bits 59 to 63 in a Leaf Page Table Entry to configure the Memory Type: Cacheable / Bufferable / Strongly-Ordered. For the upcoming port of NuttX to PINE64 Ox64 BL808 SBC, we need to set the Memory Type to Strongly-Ordered for I/O Memory, which requires 64-bit MMU Flags.
Details of C906 MMU: https://lupyuen.github.io/articles/plic3#t-head-errata
Newer RISC-V Cores will use the Svpbmt Extension to configure the Memory Type (Cacheable / Strongly-Ordered). Svpbmt uses Bits 61 to 62 in a Leaf Page Table Entry to define the Memory Type. This also requires 64-bit MMU Flags.
Details of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/main/src/supervisor.adoc#svpbmt
Usage:
1. CONFIG_FS_PROCFS_MAX_STACK_RECORD > 0, such as 32,
2. add '-finstrument-functions' to CFLAGS for What you want to check
stack.
3. mount porcfs
4. cat /proc/<pid>/stack will print backtace & size
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Add registration function instrumentation API,
which can achieve instrumentation of entering and
exiting functions through the compiler's functionality.
We can use CONFIG_ARCH_INSTRUMENT_ALL to add instrumentation for all
source, or add '-finstrument-functions' to CFLAGS for Part of the
source.
Notice:
1. use CONFIG_ARCH_INSTRUMENT_ALL must mark _start or entry noinstrument_function,
becuase bss not set.
2. Make sure your callbacks are not instrumented recursively.
use instrument_register to register entry function and exit function.
They will be called by the instrumented function
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Virtio driver can used this api to judge whether the this feature
is supported by both virtio driver and device.
Signed-off-by: Bowen Wang <wangbowen6@xiaomi.com>
Binary nibble to/from ascii hex conversion was buggy on both
lib_slcdencode and lib_slcddecode libraries.
This bug caused the slcd library to fail to decode 5-byte sequence command
which have 'count' argument value bigger than 0x9.
Signed-off-by: Federico Braghiroli <federico.braghiroli@gmail.com>
Revert "ci/docker: Fix " Could not find GN_EXECUTABLEXX using the following names: gn""
This reverts commit d6ac9e1aed.
Revert "tools/ci: Skip copy gn temporary files"
This reverts commit 4673fccece.
