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fe7d8c941c
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13490 Commits

Author SHA1 Message Date
Jussi Kivilinna
fe7d8c941c stm32f7: do not enable read-modify-write on DTCM. "AN 4667 - STM32F7 Series system architecture and performance" recommends to disable read-modify-write on DTCM: "If the DTCM-RAM is used as data location and the variables used are byte or/and halfword types, since there is no ECC management in this RAM on the STM32F7 Series, it is recommended to disable the read-modify-write of the DTCM-RAM in the DTCM interface (inthe DTCMCR register) to increase the performance." 2017-09-01 08:01:54 -06:00
Juha Niskanen
258fa08e69 STM32L4 DAC: Fix naming so that DAC1 and DAC2 always refer to channels 1 and 2 
User should not be bothered by details like how many IP blocks there are. As no
current STM32L4 has second DAC block (channel 3), remove support for such
hypothetical hardware. DMA channels corrected.

Change-Id: I2cba7e55803871f1ff945538113f12cf5088f68d
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-09-01 10:01:03 +03:00
Juha Niskanen
0003ad171d STM32L4 DAC: separate DMA buffer configuration for channels 
Change-Id: Ibc6dc90b39b784b5534b8908eaf615bf1ddcb7ed
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-09-01 10:00:55 +03:00
Juha Niskanen
4025205772 STM32L4 DAC: add option for routing DAC output to ADC 
Actually write something to the DAC DMA buffer.

Change-Id: I1b2516ac26fb17f5242611b56be8926c5f40c2c7
Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
 2017-09-01 10:00:46 +03:00
Gregory Nutt
91d473b816 Revert "stm32 FLASH allow non blocking operation on constrained devices" 
This reverts commit ad2ef95ddf.
 2017-08-31 15:14:26 -06:00
David Sidrane
9fc283526a Merged in david_s5/nuttx/master_stm32_flash (pull request #474) 
stm32 FLASH allow non blocking operation on constrained devices

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-08-31 18:04:07 +00:00
Sergey Ustinov
8c35b2ddca Add the set counter function for stm32 timers 2017-08-31 11:54:00 -06:00
David Sidrane
ad2ef95ddf stm32 FLASH allow non blocking operation on constrained devices 
On a very memory constrained device with a single task. The
   sem_wait and sem_post operations can be disabled, to save space.
   The default is blocking enabled.
 2017-08-31 07:47:37 -10:00
Sergei Ustinov
795650a2fb I'm worried about the stm32_tim_getcounter funtion. It returns always 32 bits. But major stm32 timers have 16 bits counters. I think, it's not a good idea to return the memory behind the TIMx_CNT register. This changes adds the register size checking. 2017-08-31 11:45:28 -06:00
Gregory Nutt
a7fd8eb203 Trivial removal of a blank line. 2017-08-31 11:36:18 -06:00
Gregory Nutt
27cfde9968 Protected/Kernel Builds: Review us of kmm_addregion vs. kumm_addregsion in other configurations. 2017-08-31 08:49:21 -06:00
Gregory Nutt
69f1399aa7 LPC43xx: Add external RAM to the user heap, not the kernel heap. 2017-08-31 08:12:42 -06:00
Alan Carvalho de Assis
ef3898c2dd LPC43xx: Modify up_allocate_(k)heap() to support PROTECTED mode 2017-08-31 07:58:16 -06:00
Gregory Nutt
9d3b1af1cd ARM syscall logic: Clear bit 0 in PC settings. Bit 0 is the thumb mode indication and should not be set in the PC. 2017-08-30 13:56:03 -06:00
raiden00pl
85c48de040 stm32_hrtim: add DMA configuration 2017-08-28 17:44:14 +02:00
Juha Niskanen
809569cda9 STM32L4 ADC: implement peripheral 2017-08-28 07:05:33 -06:00
Juha Niskanen
a2dc88e075 STM32, STM32L4, STM32F7 ADC: fix channel 18 sample time 2017-08-28 07:05:33 -06:00
Juha Niskanen
e8cd2f88b8 STM32L4 RCC: enable ADC clock source 2017-08-28 07:05:32 -06:00
Alan Carvalho de Assis
81d6cefd65 Add support to STM32F433RC 2017-08-28 07:05:32 -06:00
raiden00pl
5695a55569 stm32_dac.c: support external triggering for DMA transfer 2017-08-27 18:25:55 +02:00
Mateusz Szafoni
ea35f31f73 Merged in raiden00/nuttx (pull request #469) 
Master

* stm32f0/Kconfig: remove references to HRTIM

* STM32F33: missing SYSCFG CFGR3 definitions

* stm32_hrtim.h: remove redundant definitions

* stm32_hrtim.c: fix DAC triggers configuration

* stm32_hritm.c: warning message when default value selected

* stm32_hrtim.c: missing master timer logic

* stm32_hrtim.c: add more assertions

* stm32_dac.c: fix conditional

* stm32_dac.c: conditional logic for timer triggering

* stm32_dac.c: fix TSEL configuration when HRTIM

* stm32_dac.c: unnecessary condition

* stm32_dac.c: DMA request remapping

* stm32_dac.c: fix commpilation errors

* stm32_dac.c: add DMA buffers initialization logic

* stm32_hrtim.c: enable DAC triggering

* analog/comp.c: fix compilation errors when poll disabled

* stm32_hrtim.c: remove doubled assertions

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-08-27 12:49:53 +00:00
Gregory Nutt
7858ed834b Minor, cosmetic changes from review of last comment. 2017-08-27 06:48:42 -06:00
Masayuki Ishikawa
cc9c8260f0 arch/arm/src/lc823450: Add eMMC/SD and USB support 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2017-08-27 19:11:07 +09:00
Masayuki Ishikawa
56bf5b2a98 arch/arm/src/lc823450: Conform to the NuttX coding style 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
 2017-08-27 19:11:03 +09:00
Gregory Nutt
f43f372823 Update some comments. 2017-08-26 11:50:41 -06:00
Nickolay Semyonov (RPI)
1fcc7ec38e Ommitted a file in previous commit 2017-08-26 11:45:08 -06:00
Gregory Nutt
48c27f8ffc Simulator: Adds necessary functionality to build Simulator under ARM Linux. Tested only on Raspberry3. Currently setjmp/longjmp do not save/restore floating point registers. Patch provided by Bitbucket user nbkolchin. 2017-08-26 11:38:44 -06:00
Juha Niskanen
1be5f0a3fc STM32L4 COMP: comparators share RCC enable bit with SYSCFG 2017-08-25 07:06:39 -06:00
Juha Niskanen
1152e4868b STM32L4 DAC: report transfer as completed in DMA callback. Without this even O_NONBLOCK writes block the calling task if DAC was using DMA. 2017-08-25 07:05:11 -06:00
Juha Niskanen
874947d7e5 STM32L4 TIM: TIM15,16,17 are always in APB2 2017-08-25 07:02:21 -06:00
Gregory Nutt
dc8f3778a9 drivers/sensors: Fix more naming of configurations to be compliant for two more drivers. Still a few more to go. 2017-08-24 10:26:53 -06:00
Jussi Kivilinna
310a29227a drivers/lcd: add DD-12864WO-4A/SSD1309 support to SSD1306 driver 2017-08-22 08:32:52 -06:00
Juha Niskanen
d7ae3d74c3 STM32L4 ADC: correct EXTSEL macros 2017-08-22 06:49:48 -06:00
Pekka Ervasti
6b1ccef2f9 STM32L4 COMP: bind to upper half comp driver 2017-08-22 06:47:57 -06:00
raiden00pl
a5997cb186 stm32_dac: add support for HRTIM triggering 2017-08-21 19:46:18 +02:00
raiden00pl
a5f3a5848d stm32_dac.c typo 2017-08-21 18:59:21 +02:00
raiden00pl
db7a94288f stm32f33xxx_dma.h: typos 2017-08-21 18:50:07 +02:00
raiden00pl
b460f2bca1 stm32f10xxx_dma.h: fix DAC names and remove STM32F33 section 2017-08-21 18:50:07 +02:00
raiden00pl
104ff2b5d8 stm32_dac: separate dma buffer configuration for channels 2017-08-21 18:50:07 +02:00
Juha Niskanen
37867ae3b9 chip.h edited online with Bitbucket: correct some STM32_NDAC 2017-08-21 07:30:58 +00:00
Mateusz Szafoni
ccd421b158 stm32_dac.c edited online with Bitbucket 2017-08-20 18:47:44 +00:00
raiden00pl
04743f3e77 stm32_dac: change name convention. Previous naming was confusing 2017-08-20 20:19:53 +02:00
raiden00pl
0bed6ac8b4 STM32F33: correct STM32_NDAC 2017-08-20 20:07:50 +02:00
raiden00pl
a8e8862ef9 stm32_dac.c: fix some configuration logic. When STM32_NDAC is greather than 1, then second channel is always DAC1OUT2. 2017-08-20 19:02:56 +02:00
raiden00pl
1479fd6075 stm32_comp: add default INM configuration and some missing COMP1,3,5,7 code 2017-08-20 10:45:55 +02:00
raiden00pl
30ebd32ab4 stm32f33xxx_pinmap.h: missing define 2017-08-20 10:45:55 +02:00
raiden00pl
241c42447f stm32f33xxx_comp.h: typos 2017-08-20 10:45:55 +02:00
raiden00pl
01c98df18c STM32F33: remove redundant DAC file 2017-08-20 10:45:55 +02:00
David Sidrane
b594d43d24 Merged in david_s5/nuttx/upstream_dma_dcache_fix (pull request #462) 
STM32F7:SDMMC, DMA dcache check in stm32_dmacapable and  SDMMC stm32_dma{recv|send}setup

Approved-by: Gregory Nutt <gnutt@nuttx.org>
 2017-08-17 20:14:24 +00:00
David Sidrane
ef42c25140 stm32f7:SDMMC add dcache alignment check in dma{recv|send}setup 
In the where CONFIG_SDIO_PREFLIGHT is not used and
   dcache write-buffed mode is used (not write-through)
   buffer alignment is required for DMA transfers because
   a) arch_invalidate_dcache could lose buffered writes data
   and b) arch_flush_dcache could corrupt adjacent memory if
   the buffer and the bufflen, are not on ARMV7M_DCACHE_LINESIZE
   boundaries.
 2017-08-17 09:51:37 -10:00