/**************************************************************************** * boards/arm/stm32/nucleo-f4x1re/include/nucleo-f401re.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * ****************************************************************************/ #ifndef __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_NUCLEO_F401RE_H #define __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_NUCLEO_F401RE_H /**************************************************************************** * Included Files ****************************************************************************/ #include #ifndef __ASSEMBLY__ # include #endif /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ /* Clocking *****************************************************************/ /* The NUCLEO401RE supports both HSE and LSE crystals (X2 and X3). * However, as shipped, the X2 and X3 crystals are not populated. * Therefore the Nucleo-F401RE will need to run off the 16MHz HSI clock. * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 84000000 Determined by PLL * configuration * HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE) * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) * HSI Frequency(Hz) : 16000000 (nominal) * PLLM : 16 (STM32_PLLCFG_PLLM) * PLLN : 336 (STM32_PLLCFG_PLLN) * PLLP : 4 (STM32_PLLCFG_PLLP) * PLLQ : 7 (STM32_PLLCFG_PPQ) * Flash Latency(WS) : 5 * Prefetch Buffer : OFF * Instruction cache : ON * Data cache : ON * Require 48MHz for USB OTG FS, : Enabled * SDIO and RNG clock */ /* HSI - 16 MHz RC factory-trimmed * LSI - 32 KHz RC * HSE - not installed * LSE - not installed */ #define STM32_HSI_FREQUENCY 16000000ul #define STM32_LSI_FREQUENCY 32000 #define STM32_BOARD_USEHSI 1 /* Main PLL Configuration. * * Formulae: * * VCO input frequency = PLL input clock frequency / PLLM, * 2 <= PLLM <= 63 * VCO output frequency = VCO input frequency × PLLN, * 192 <= PLLN <= 432 * PLL output clock frequency = VCO frequency / PLLP, * PLLP = 2, 4, 6, or 8 * USB OTG FS clock frequency = VCO frequency / PLLQ, * 2 <= PLLQ <= 15 * * We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz. * Some possible solutions include: * * PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 * PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 * PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 * PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 * PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 * PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 * * We will configure like this * * PLL source is HSI * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN * = (16,000,000 / 16) * 336 * = 336,000,000 * SYSCLK = PLL_VCO / PLLP * = 336,000,000 / 4 = 84,000,000 * USB OTG FS and SDIO Clock * = PLL_VCO / PLLQ * = 336,000,000 / 7 = 48,000,000 * * REVISIT: Trimming of the HSI is not yet supported. */ #define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) #define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) #define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 #define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) #define STM32_SYSCLK_FREQUENCY 84000000ul /* AHB clock (HCLK) is SYSCLK (84MHz) */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/2 (42MHz) */ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT */ #define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (84MHz) */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT */ #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ /* REVISIT */ #define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) #define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) #define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) #define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) #define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) #define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) #define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) #define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses * to service FIFOs in interrupt driven mode. These values have not been * tuned!!! * * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz */ /* REVISIT */ #define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz */ /* REVISIT */ #ifdef CONFIG_SDIO_DMA # define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) #else # define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) #endif /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz */ /* REVISIT */ #ifdef CONFIG_SDIO_DMA # define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) #else # define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) #endif /**************************************************************************** * Public Data ****************************************************************************/ #ifndef __ASSEMBLY__ #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" extern "C" { #else #define EXTERN extern #endif /**************************************************************************** * Public Function Prototypes ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) } #endif #endif /* __ASSEMBLY__ */ #endif /* __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_NUCLEO_F401RE_H */