/***************************************************************************** * boards/arm/lpc17xx_40xx/pnev5180b/scripts/flash.ld * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Michael Jung * * Based on boards/zkit-arm-1769/scripts/flash.ld * * Copyright (C) 2013 Zilogic Systems. All rights reserved. * Author: BabuSubashChandar * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * 3. Neither the name NuttX nor the names of its contributors may be * used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * *****************************************************************************/ /* The LPC1769 has 512Kb of FLASH beginning at address 0x0000:0000 and * 64Kb of total SRAM: 32Kb of SRAM in the CPU block beginning at address * 0x10000000 and 32Kb of AHB SRAM in two banks of 16Kb beginning at addresses * 0x20070000 and 0x20080000. Here we assume that .data and .bss will all fit * into the 32Kb CPU SRAM address range. */ MEMORY { flash (rx) : ORIGIN = 0x00000000, LENGTH = 512K sram (rwx) : ORIGIN = 0x10000000, LENGTH = 32K } OUTPUT_ARCH(arm) ENTRY(_stext) SECTIONS { .text : { _stext = ABSOLUTE(.); *(.vectors) *(.text .text.*) *(.fixup) *(.gnu.warning) *(.rodata .rodata.*) *(.gnu.linkonce.t.*) *(.glue_7) *(.glue_7t) *(.got) *(.gcc_except_table) *(.gnu.linkonce.r.*) _etext = ABSOLUTE(.); } > flash _eronly = ABSOLUTE(.); .data : { _sdata = ABSOLUTE(.); *(.data .data.*) *(.gnu.linkonce.d.*) CONSTRUCTORS _edata = ABSOLUTE(.); } > sram AT > flash .ARM.extab : { *(.ARM.extab*) } >sram __exidx_start = ABSOLUTE(.); .ARM.exidx : { *(.ARM.exidx*) } >sram __exidx_end = ABSOLUTE(.); .bss : { _sbss = ABSOLUTE(.); *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); _ebss = ABSOLUTE(.); } > sram /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } .stab.exclstr 0 : { *(.stab.exclstr) } .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_info 0 : { *(.debug_info) } .debug_line 0 : { *(.debug_line) } .debug_pubnames 0 : { *(.debug_pubnames) } .debug_aranges 0 : { *(.debug_aranges) } }