/************************************************************************************ * configs/nucleo-h743zi/include/board.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * Simon Laube * Mateusz Szafoni * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * 3. Neither the name NuttX nor the names of its contributors may be * used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * ************************************************************************************/ #ifndef __CONFIG_NUCLEO_H743ZI_INCLUDE_BOARD_H #define __CONFIG_NUCLEO_H743ZI_INCLUDE_BOARD_H /************************************************************************************ * Included Files ************************************************************************************/ #include #ifndef __ASSEMBLY__ # include #endif /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ /* The Nucleo-144 board provides the following clock sources: * * MCO: 8 MHz from MCO output of ST-LINK is used as input clock * X2: 32.768 KHz crystal for LSE * X3: HSE crystal oscillator (not provided) * * So we have these clock source available within the STM32 * * HSI: 16 MHz RC factory-trimmed * LSI: 32 KHz RC * HSE: 8 MHz from MCO output of ST-LINK * LSE: 32.768 kHz */ #define STM32_BOARD_XTAL 8000000ul #define STM32_HSI_FREQUENCY 16000000ul #define STM32_LSI_FREQUENCY 32000 #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* Main PLL Configuration. * * PLL source is HSE = 8,000,000 * * To use HSE, configure the solder bridges on the board: * * - SB148, SB8 and SB9 OFF * - SB112 and SB149 ON * * When STM32_HSE_FREQUENCY / PLLM <= 2MHz VCOL must be selected. VCOH otherwise. * * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN * Subject to: * * 1 <= PLLM <= 63 * 4 <= PLLN <= 512 * 150 MHz <= PLL_VCOL <= 420MHz * 192 MHz <= PLL_VCOH <= 836MHz * * SYSCLK = PLL_VCO / PLLP * CPUCLK = SYSCLK / D1CPRE * Subject to * * PLLP1 = {2, 4, 6, 8, ..., 128} * PLLP2,3 = {2, 3, 4, ..., 128} * CPUCLK <= 400 MHz */ #define STM32_BOARD_USEHSE #define STM32_HSEBYP_ENABLE #define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE /* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR * * PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz * * PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz * PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz * PLL1R = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz */ #define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \ RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \ RCC_PLLCFGR_DIVP1EN | \ RCC_PLLCFGR_DIVQ1EN | \ RCC_PLLCFGR_DIVR1EN) #define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2) #define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(200) #define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) #define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) #define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8) #define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200) #define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) #define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) #define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8) /* PLL2 */ #define STM32_PLLCFG_PLL2CFG 0 #define STM32_PLLCFG_PLL2M 0 #define STM32_PLLCFG_PLL2N 0 #define STM32_PLLCFG_PLL2P 0 #define STM32_PLLCFG_PLL2Q 0 #define STM32_PLLCFG_PLL2R 0 #define STM32_VCO2_FREQUENCY #define STM32_PLL2P_FREQUENCY #define STM32_PLL2Q_FREQUENCY #define STM32_PLL2R_FREQUENCY /* PLL3 */ #define STM32_PLLCFG_PLL3CFG 0 #define STM32_PLLCFG_PLL3M 0 #define STM32_PLLCFG_PLL3N 0 #define STM32_PLLCFG_PLL3P 0 #define STM32_PLLCFG_PLL3Q 0 #define STM32_PLLCFG_PLL3R 0 #define STM32_VCO3_FREQUENCY #define STM32_PLL3P_FREQUENCY #define STM32_PLL3Q_FREQUENCY #define STM32_PLL3R_FREQUENCY /* SYSCLK = PLL1P = 400 MHz * CPUCLK = SYSCLK / 1 = 400 MHz */ #define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) #define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1) /* Configure Clock Assignments */ /* AHB clock (HCLK) is SYSCLK/2 (200 MHz max) * HCLK1 = HCLK2 = HCLK3 = HCLK4 */ #define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */ #define STM32_ACLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */ #define STM32_HCLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */ #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ /* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */ #define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) /* APB2 clock (PCLK2) is HCLK/4 (54 MHz) */ #define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd4 /* PCLK2 = HCLK / 4 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/4) /* APB3 clock (PCLK3) is HCLK/4 (54 MHz) */ #define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd4 /* PCLK3 = HCLK / 4 */ #define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/4) /* APB4 clock (PCLK4) is HCLK/4 (54 MHz) */ #define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd4 /* PCLK4 = HCLK / 4 */ #define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/4) /* Kernel Clock Configuration * * Note: look at Table 54 in ST Manual */ /* I2C123 clock source - HSI */ #define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI /* I2C4 clock source - HSI */ #define STM32_RCC_D2CCIP3R_I2C4SRC RCC_D2CCIP3R_I2C4SEL_HSI /* SPI123 clock source - PLL1 */ #define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1 /* SPI45 clock source - APB (PCLK2?) */ #define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_APB /* SPI6 clock source - APB (PCLK4) */ #define STM32_RCC_D3CCIP1R_SPI6SRC RCC_D3CCIP1R_SPI6SEL_PCLK4 /* FLASH wait states * * ------------ ---------- ----------- * Vcore MAX ACLK WAIT STATES * ------------ ---------- ----------- * 1.15-1.26 V 70 MHz 0 * (VOS1 level) 140 MHz 1 * 210 MHz 2 * 1.05-1.15 V 55 MHz 0 * (VOS2 level) 110 MHz 1 * 165 MHz 2 * 220 MHz 3 * 0.95-1.05 V 45 MHz 0 * (VOS3 level) 90 MHz 1 * 135 MHz 2 * 180 MHz 3 * 225 MHz 4 * ------------ ---------- ----------- */ #define BOARD_FLASH_WAITSTATES 4 /* LED definitions ******************************************************************/ /* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue * LED and LD3 a Red LED, that can be controlled by software. The following * definitions assume the default Solder Bridges are installed. * * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way. * The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ #define BOARD_LED1 0 #define BOARD_LED2 1 #define BOARD_LED3 2 #define BOARD_NLEDS 3 #define BOARD_LED_GREEN BOARD_LED1 #define BOARD_LED_BLUE BOARD_LED2 #define BOARD_LED_RED BOARD_LED3 /* LED bits for use with board_userled_all() */ #define BOARD_LED1_BIT (1 << BOARD_LED1) #define BOARD_LED2_BIT (1 << BOARD_LED2) #define BOARD_LED3_BIT (1 << BOARD_LED3) /* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in * include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related * events as follows: * * * SYMBOL Meaning LED state * Red Green Blue * ---------------------- -------------------------- ------ ------ ----*/ #define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ #define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ #define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ #define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ #define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ #define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ #define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ #define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ #define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */ /* Thus if the Green LED is statically on, NuttX has successfully booted and * is, apparently, running normally. If the Red LED is flashing at * approximately 2Hz, then a fatal error has been detected and the system * has halted. */ /* Button definitions ***************************************************************/ /* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is * connected to GPIO PI11. A high value will be sensed when the button is depressed. */ #define BUTTON_USER 0 #define NUM_BUTTONS 1 #define BUTTON_USER_BIT (1 << BUTTON_USER) /* Alternate function pin selections ************************************************/ /* USART3 (Nucleo Virtual Console) */ #define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */ #define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */ /* USART6 (Arduino Serial Shield) */ #define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */ #define GPIO_USART6_TX GPIO_USART6_TX_2 /* PG14 */ /* I2C1 Use Nucleo I2C pins */ #define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 */ #define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 */ /* SPI3 */ #define GPIO_SPI3_MISO GPIO_SPI3_MISO_1 /* PB4 */ #define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_4 /* PB5 */ #define GPIO_SPI3_SCK GPIO_SPI3_SCK_1 /* PB3 */ #define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 /* PA4 */ /************************************************************************************ * Public Data ************************************************************************************/ #ifndef __ASSEMBLY__ #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" extern "C" { #else #define EXTERN extern #endif /************************************************************************************ * Public Function Prototypes ************************************************************************************/ #undef EXTERN #if defined(__cplusplus) } #endif #endif /* __ASSEMBLY__ */ #endif /* __CONFIG_NUCLEO_H743ZI_INCLUDE_BOARD_H */