# # For a description of the syntax of this configuration file, # see the file kconfig-language.txt in the NuttX tools repository. # if ARCH_RISCV comment "RISC-V Options" choice prompt "RISC-V chip selection" default ARCH_CHIP_RISCV_CUSTOM config ARCH_CHIP_FE310 bool "SiFive FE310" select ARCH_RV32IM ---help--- SiFive FE310 processor (E31 RISC-V Core with MAC extensions). config ARCH_CHIP_K210 bool "Kendryte K210" select ARCH_RV64GC select ARCH_HAVE_MPU select ARCH_HAVE_TESTSET select ARCH_HAVE_MULTICPU ---help--- Kendryte K210 processor (RISC-V 64bit core with GC extensions) config ARCH_CHIP_LITEX bool "Enjoy Digital LITEX VEXRISCV" select ARCH_RV32IM ---help--- Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA). config ARCH_CHIP_BL602 bool "BouffaloLab BL602" select ARCH_RV32IM select ARCH_HAVE_FPU select ARCH_HAVE_RESET ---help--- BouffaloLab BL602(rv32imfc) config ARCH_CHIP_ESP32C3 bool "Espressif ESP32-C3" select ARCH_RV32IM select RV32IM_HW_MULDIV select ARCH_VECNOTIRQ select ARCH_HAVE_RESET select LIBC_ARCH_ATOMIC select LIBC_ARCH_MEMSET select LIBC_ARCH_MEMCPY select LIBC_ARCH_MEMMOVE select LIBC_ARCH_MEMCMP select LIBC_ARCH_MEMCHR select LIBC_ARCH_STRCPY select LIBC_ARCH_STRCHR select LIBC_ARCH_STRCMP select LIBC_ARCH_STRLCPY select LIBC_ARCH_STRNCPY select LIBC_ARCH_STRLEN select LIBC_ARCH_STRNLEN select ARCH_HAVE_TEXT_HEAP select ARCH_HAVE_BOOTLOADER ---help--- Espressif ESP32-C3 (RV32IMC). config ARCH_CHIP_C906 bool "THEAD C906" select ARCH_RV64GC select ARCH_HAVE_MPU ---help--- THEAD C906 processor (RISC-V 64bit core with GCVX extensions). config ARCH_CHIP_MPFS bool "MicroChip Polarfire (MPFS)" select ARCH_RV64GC select ARCH_HAVE_MPU select ARCH_HAVE_RESET select ARCH_HAVE_SPI_CS_CONTROL select ARCH_HAVE_PWM_MULTICHAN ---help--- MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions). config ARCH_CHIP_RV32M1 bool "NXP RV32M1" select ARCH_RV32IM ---help--- NXP RV32M1 processor (RISC-V Core with PULP extensions). config ARCH_CHIP_QEMU_RV32 bool "QEMU RV32" select ARCH_RV32IM ---help--- QEMU Generic RV32 processor config ARCH_CHIP_RISCV_CUSTOM bool "Custom RISC-V chip" select ARCH_CHIP_CUSTOM ---help--- Select this option if there is no directory for the chip under arch/risc-v/src/. endchoice config ARCH_RV32I bool default n select ARCH_HAVE_SETJMP config ARCH_RV32IM bool default n select ARCH_HAVE_SETJMP config ARCH_RV64GC bool default n select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF select ARCH_HAVE_SETJMP config ARCH_FAMILY string default "rv32im" if ARCH_RV32IM default "rv64gc" if ARCH_RV64GC config ARCH_CHIP string default "fe310" if ARCH_CHIP_FE310 default "k210" if ARCH_CHIP_K210 default "litex" if ARCH_CHIP_LITEX default "bl602" if ARCH_CHIP_BL602 default "esp32c3" if ARCH_CHIP_ESP32C3 default "c906" if ARCH_CHIP_C906 default "mpfs" if ARCH_CHIP_MPFS default "rv32m1" if ARCH_CHIP_RV32M1 default "qemu-rv32" if ARCH_CHIP_QEMU_RV32 config ARCH_RISCV_INTXCPT_EXTENSIONS bool "RISC-V Integer Context Extensions" default n ---help--- RISC-V could be customized with extensions. Some Integer Context Registers have to be saved and restored when Contexts switch. if ARCH_RISCV_INTXCPT_EXTENSIONS config ARCH_RISCV_INTXCPT_EXTREGS int "Number of Extral RISC-V Integer Context Registers" default 0 endif if ARCH_RV32IM source "arch/risc-v/src/rv32im/Kconfig" endif if ARCH_RV64GC source "arch/risc-v/src/rv64gc/Kconfig" endif if ARCH_CHIP_FE310 source "arch/risc-v/src/fe310/Kconfig" endif if ARCH_CHIP_K210 source "arch/risc-v/src/k210/Kconfig" endif if ARCH_CHIP_LITEX source "arch/risc-v/src/litex/Kconfig" endif if ARCH_CHIP_BL602 source "arch/risc-v/src/bl602/Kconfig" endif if ARCH_CHIP_ESP32C3 source "arch/risc-v/src/esp32c3/Kconfig" endif if ARCH_CHIP_C906 source "arch/risc-v/src/c906/Kconfig" endif if ARCH_CHIP_MPFS source "arch/risc-v/src/mpfs/Kconfig" endif if ARCH_CHIP_RV32M1 source "arch/risc-v/src/rv32m1/Kconfig" endif if ARCH_CHIP_QEMU_RV32 source "arch/risc-v/src/qemu-rv32/Kconfig" endif endif