/**************************************************************************** * boards/arm/stm32/photon/include/board.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * ****************************************************************************/ #ifndef __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H #define __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H /**************************************************************************** * Included Files ****************************************************************************/ #include #ifndef __ASSEMBLY__ # include #endif /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ /* Clocking *****************************************************************/ /* The Particle photon board features a single 26MHz crystal. * * This is the canonical configuration: * System Clock source : PLL (HSE) * SYSCLK(Hz) : 120000000 Determined by PLL * configuration * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) * HSE Frequency(Hz) : 26000000 (STM32_BOARD_XTAL) * PLLM : 26 (STM32_PLLCFG_PLLM) * PLLN : 240 (STM32_PLLCFG_PLLN) * PLLP : 2 (STM32_PLLCFG_PLLP) * PLLQ : 5 (STM32_PLLCFG_PLLQ) * Main regulator output voltage : Scale1 mode Needed for high speed * SYSCLK * Flash Latency(WS) : 3 * Prefetch Buffer : OFF * Instruction cache : ON * Data cache : ON * Require 48MHz for USB OTG HS : Enabled * SDIO and RNG clock */ /* HSI - 16 MHz RC factory-trimmed * LSI - 32 KHz RC * HSE - On-board crystal frequency is 26MHz * LSE - 32.768 kHz */ #define STM32_BOARD_XTAL 26000000ul #define STM32_HSI_FREQUENCY 16000000ul #define STM32_LSI_FREQUENCY 32000 #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* Main PLL Configuration. * * PLL source is HSE * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN * = (26,000,000 / 26) * 240 * = 240,000,000 * SYSCLK = PLL_VCO / PLLP * = 240,000,000 / 2 = 120,000,000 * USB OTG FS, SDIO and RNG Clock * = PLL_VCO / PLLQ * = 48,000,000 */ #define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26) #define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) #define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 #define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) #define STM32_SYSCLK_FREQUENCY 120000000ul /* AHB clock (HCLK) is SYSCLK (120MHz) */ #define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) /* Timers driven from APB1 will be twice PCLK1 */ #define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) /* Timers driven from APB2 will be twice PCLK2 */ #define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ #define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY /* USB OTG HS definitions ***************************************************/ /* Do not enable external PHY clock or OTG_HS module will not work */ #undef BOARD_ENABLE_USBOTG_HSULPI /* LED definitions **********************************************************/ /* LEDs * * A single LED is available driven by PA13. */ /* LED index values for use with board_userled() */ #define BOARD_LED1 0 #define BOARD_NLEDS 1 /* LED bits for use with board_userled_all() */ #define BOARD_LED1_BIT (1 << BOARD_LED1) /* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is * defined. In that case, the usage by the board port is defined in * include/board.h and src/sam_autoleds.c. The LEDs are used to encode * OS-related events as follows: * * ------------------- ---------------------------- ------ * SYMBOL Meaning LED * ------------------- ---------------------------- ------ */ #define LED_STARTED 0 /* NuttX has been started OFF */ #define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ #define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ #define LED_STACKCREATED 1 /* Idle stack created ON */ #define LED_INIRQ 2 /* In an interrupt N/C */ #define LED_SIGNAL 2 /* In a signal handler N/C */ #define LED_ASSERTION 2 /* An assertion failed N/C */ #define LED_PANIC 3 /* The system has crashed FLASH */ #undef LED_IDLE /* MCU is is sleep mode Not used */ /* Thus if LED is statically on, NuttX has successfully booted and is, * apparently, running normally. If LED is flashing at approximately * 2Hz, then a fatal error has been detected and the system has halted. */ /* TIM */ #define GPIO_TIM2_CH2OUT GPIO_TIM2_CH2OUT_1 #define GPIO_TIM2_CH3OUT GPIO_TIM2_CH3OUT_1 #define GPIO_TIM2_CH4OUT GPIO_TIM2_CH4OUT_1 /* RGB LED * * R = TIM2 CH2 on PA1 | G = TIM2 CH3 on PA2 | B = TIM4 CH4 on PA3 * * Note: Pin boards: GPIO_TIM2_CH2OUT ; GPIO_TIM2_CH3OUT ; GPIO_TIM2_CH4OUT */ #define RGBLED_RPWMTIMER 2 #define RGBLED_RPWMCHANNEL 2 #define RGBLED_GPWMTIMER 2 #define RGBLED_GPWMCHANNEL 3 #define RGBLED_BPWMTIMER 2 #define RGBLED_BPWMCHANNEL 4 /* Button definitions *******************************************************/ #define BOARD_BUTTON1 0 #define NUM_BUTTONS 1 #define BOARD_BUTTON1_BIT (1 << BOARD_BUTTON1) /* Alternate function pin selections ****************************************/ /* UART1 */ #ifdef CONFIG_STM32_USART1 # define GPIO_USART1_RX GPIO_USART1_RX_1 # define GPIO_USART1_TX GPIO_USART1_TX_1 #endif /* SPI1 */ #define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */ #define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 /* PA7 */ #define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */ /* SPI3 */ #define GPIO_SPI3_MISO GPIO_SPI3_MISO_1 /* PB4 */ #define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_1 /* PB5 */ #define GPIO_SPI3_SCK GPIO_SPI3_SCK_1 /* PB3 */ /* SDIO definitions *********************************************************/ /* Note that slower clocking is required when DMA is disabled in order * to avoid RX overrun/TX underrun errors due to delayed responses * to service FIFOs in interrupt driven mode. * * These values have not been tuned!!! * * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz */ #define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) /* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz */ #ifdef CONFIG_SDIO_DMA # define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) #else # define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) #endif /* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz */ #ifdef CONFIG_SDIO_DMA # define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) #else # define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) #endif /* DMA Channel/Stream Selections ********************************************/ /* Stream selections are arbitrary for now but might become important in the * future if we set aside more DMA channels/streams. * * SDIO DMA * DMAMAP_SDIO_1 = Channel 4, Stream 3 * DMAMAP_SDIO_2 = Channel 4, Stream 6 */ #define DMAMAP_SDIO DMAMAP_SDIO_1 #endif /* __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H */