/*****************************************************************************
 * arch/arm/include/cxd56xx/chip.h
 *
 *   Copyright 2018 Sony Semiconductor Solutions Corporation
 *
 *   Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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 *
 ****************************************************************************/

#ifndef __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H
#define __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H

/****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/

#define CXD56M4_SYSH_PRIORITY_MIN     0xe0 /* All bits[7:5] set is minimum priority */
#define CXD56M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define CXD56M4_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
#define CXD56M4_SYSH_PRIORITY_STEP    0x20 /* Steps between priorities */

#define NVIC_SYSH_PRIORITY_MIN        CXD56M4_SYSH_PRIORITY_MIN
#define NVIC_SYSH_PRIORITY_DEFAULT    CXD56M4_SYSH_PRIORITY_DEFAULT
#define NVIC_SYSH_PRIORITY_MAX        CXD56M4_SYSH_PRIORITY_MAX
#define NVIC_SYSH_PRIORITY_STEP       CXD56M4_SYSH_PRIORITY_STEP

/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
 * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
 * interrupts will not have execution priority.  SVCall must have execution
 * priority in all cases.
 *
 * In the normal cases, interrupts are not nest-able and all interrupts run
 * at an execution priority between NVIC_SYSH_PRIORITY_MIN and
 * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
 *
 * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
 * high priority interrupts are supported.  These are not "nested" in the
 * normal sense of the word.  These high priority interrupts can interrupt
 * normal processing but execute outside of OS (although they can "get back
 * into the game" via a PendSV interrupt).
 *
 * In the normal course of things, interrupts must occasionally be disabled
 * using the up_irq_save() inline function to prevent contention in use of
 * resources that may be shared between interrupt level and non-interrupt
 * level logic.  Now the question arises, if we are using
 * CONFIG_ARCH_HIPRI_INTERRUPT=y, do we disable all interrupts except
 * SVCall (we cannot disable SVCall interrupts).  Or do we only disable the
 * "normal" interrupts?
 *
 * If we are using the BASEPRI register to disable interrupts, then the
 * answer is that we must disable ONLY the "normal interrupts".  That
 * is because we cannot disable SVCALL interrupts and we cannot permit
 * SVCAll interrupts running at a higher priority than the high priority
 * interrupts (otherwise, they will introduce jitter in the high priority
 * interrupt response time.)
 *
 * Hence, if you need to disable the high priority interrupt, you will have
 * to disable the interrupt either at the peripheral that generates the
 * interrupt or at the NVIC.  Disabling global interrupts via the BASEPRI
 * register cannot effect high priority interrupts.
 */

/* The high priority interrupt must be highest priority.  This prevents
 * SVCALL handling from adding jitter to high priority interrupt response.
 * Disabling interrupts will disable all interrupts EXCEPT SVCALL and the
 * high priority interrupts.
 */

#define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
#define NVIC_SYSH_HIGH_PRIORITY       NVIC_SYSH_PRIORITY_MAX
#define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_MAXNORMAL_PRIORITY
#define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX

#endif /* __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H */