/****************************************************************************
 * boards/arm/lpc17xx_40xx/pnev5180b/scripts/memory.ld
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 ****************************************************************************/

/* The LPC1769 has 512Kb of FLASH beginning at address 0x0000:0000 and
 * 64Kb of total SRAM: 32Kb of SRAM in the CPU block beginning at address
 * 0x10000000 and 32Kb of AHB SRAM in two banks of 16Kb beginning at addresses
 * 0x20070000 and 0x20080000.  Here we assume that .data and .bss will all fit
 * into the 32Kb CPU SRAM address range.
 */

MEMORY
{
  /* 512Kb FLASH - Leave 256Kb for application usage */

  kflash (rx)      : ORIGIN = 0x00000000, LENGTH = 128K
  uflash (rx)      : ORIGIN = 0x00020000, LENGTH = 128K

  /* 32Kb of SRAM in the CPU block - Leave 32Kb of AHB SRAM for app usage */

  ksram (rwx)      : ORIGIN = 0x10000000, LENGTH = 16K
  usram (rwx)      : ORIGIN = 0x10004000, LENGTH = 16K
}