#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_BOARD_TTGO_T5V2_ESP32

if PM

config PM_ALARM_SEC
	int "PM_STANDBY delay (seconds)"
	default 15
	depends on PM
	---help---
		Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode.

config PM_ALARM_NSEC
	int "PM_STANDBY delay (nanoseconds)"
	default 0
	depends on PM
	---help---
		Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode.

config PM_SLEEP_WAKEUP_SEC
	int "PM_SLEEP delay (seconds)"
	default 20
	depends on PM
	---help---
		Number of seconds to wait in PM_SLEEP.

config PM_SLEEP_WAKEUP_NSEC
	int "PM_SLEEP delay (nanoseconds)"
	default 0
	depends on PM
	---help---
		Number of additional nanoseconds to wait in PM_SLEEP.

endif # PM

if ESP32_SPIRAM

menu "PSRAM clock and cs IO for ESP32-DOWD"
config D0WD_PSRAM_CLK_IO
	int "PSRAM CLK IO number"
	range 0 33
	default 17
	---help---
		The PSRAM CLOCK IO can be any unused GPIO, user can config it
		based on hardware design. If user use 1.8V flash and 1.8V psram,
		this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.

config D0WD_PSRAM_CS_IO
	int "PSRAM CS IO number"
	range 0 33
	default 16
	---help---
		The PSRAM CS IO can be any unused GPIO, user can config it based
		on hardware design. If user use 1.8V flash and 1.8V psram, this
		value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
endmenu

menu "PSRAM clock and cs IO for ESP32-D2WD"
config D2WD_PSRAM_CLK_IO
	int "PSRAM CLK IO number"
	range 0 33
	default 9
	---help---
		User can config it based on hardware design. For ESP32-D2WD chip,
		the psram can only be 1.8V psram, so this value can only be one
		of 6, 7, 8, 9, 10, 11, 16, 17.

config D2WD_PSRAM_CS_IO
	int "PSRAM CS IO number"
	range 0 33
	default 10
	---help---
		User can config it based on hardware design. For ESP32-D2WD chip,
		the psram can only be 1.8V psram, so this value can only be one
		of 6, 7, 8, 9, 10, 11, 16, 17.
endmenu

menu "PSRAM clock and cs IO for ESP32-PICO"
config PICO_PSRAM_CS_IO
	int "PSRAM CS IO number"
	range 0 33
	default 10
	---help---
		The PSRAM CS IO can be any unused GPIO, user can config it based on
		hardware design.
		For ESP32-PICO chip, the psram share clock with flash, so user do
		not need to configure the clock IO.
		For the reference hardware design, please refer to
		https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
endmenu

config ESP32_SPIRAM_SPIWP_SD3_PIN
	int "SPI PSRAM WP(SD3) Pin when customising pins via eFuse (read help)"
	range 0 33
	default 7
	---help---
		This value is ignored unless flash mode is set to DIO or DOUT and
		the SPI flash pins have been overridden by setting the eFuses
		SPI_PAD_CONFIG_xxx.

		When this is the case, the eFuse config only defines 3 of the 4
		Quad I/O data pins. The WP pin (aka ESP32 pin "SD_DATA_3" or SPI
		flash pin "IO2") is not specified in eFuse. And the psram only
		has QPI mode, the WP pin is necessary, so we need to configure
		this value here.

		When flash mode is set to QIO or QOUT, the PSRAM WP pin will be
		set as the value configured in bootloader.

		For ESP32-PICO chip, the default value of this config should be 7.

endif # ESP32_PSRAM

endif # ARCH_BOARD_TTGO_T5V2_ESP32