############################################################################
# arch/arm/src/sam34/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements.  See the NOTICE file distributed with
# this work for additional information regarding copyright ownership.  The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License.  You may obtain a copy of the License at
#
#   http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################

# The start-up, "head", file

# Common ARM and Cortex-M3 files

CMN_ASRCS  = arm_saveusercontext.S arm_fullcontextrestore.S
CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S

CMN_CSRCS  = arm_assert.c arm_blocktask.c arm_createstack.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c
CMN_CSRCS += arm_memfault.c arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_unblocktask.c arm_udelay.c
CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_puts.c
CMN_CSRCS += arm_tcbinfo.c

ifneq ($(CONFIG_SMP),y)
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += arm_idle.c
endif
endif

# Configuration-dependent common files

ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += arm_lazyexception.S
else
CMN_ASRCS += arm_exception.S
endif
CMN_CSRCS += arm_vectors.c

ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif

ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif

ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif

ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
endif

ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif

# Required SAM3/4 files

CHIP_CSRCS  = sam_allocateheap.c sam_irq.c sam_lowputc.c sam_serial.c
CHIP_CSRCS += sam_start.c

# Configuration-dependent SAM3/4 files

ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_timerisr.c
endif

ifeq ($(CONFIG_CRYPTO_AES),y)
CHIP_CSRCS += sam_aes.c
endif

ifeq ($(CONFIG_ARCH_CHIP_SAM4CM),y)
CHIP_CSRCS += sam4cm_supc.c
endif

ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y)
CHIP_CSRCS += sam4l_clockconfig.c sam4l_periphclks.c sam4l_gpio.c
else
CHIP_CSRCS += sam_clockconfig.c sam_gpio.c sam_gpioirq.c
endif

ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += sam_userspace.c sam_mpuinit.c
endif

ifeq ($(CONFIG_SAM34_CMCC),y)
CHIP_CSRCS += sam_cmcc.c
endif

ifeq ($(CONFIG_SAM34_DMAC0),y)
CHIP_CSRCS += sam_dmac.c
endif

ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y)
ifeq ($(CONFIG_SAM34_PDCA),y)
CHIP_CSRCS += sam4l_pdca.c
endif
endif

ifeq ($(CONFIG_SAM34_EMAC),y)
CHIP_CSRCS += sam_emac.c
endif

ifeq ($(CONFIG_SAM34_UDP),y)
CHIP_CSRCS += sam_udp.c
endif

ifeq ($(CONFIG_SAM34_HSMCI),y)
CHIP_CSRCS += sam_hsmci.c
endif

ifeq ($(CONFIG_SAM34_EXTNAND),y)
CHIP_CSRCS += sam4s_nand.c
endif

ifeq ($(CONFIG_SAM34_SPI0),y)
CHIP_CSRCS += sam_spi.c
else
ifeq ($(CONFIG_SAM34_SPI1),y)
CHIP_CSRCS += sam_spi.c
endif
endif

ifeq ($(CONFIG_SAM34_TWIM),y)
CHIP_CSRCS += sam_twi.c
endif

ifeq ($(CONFIG_SAM34_AES),y)
CHIP_CSRCS += sam_aes.c
endif

ifeq ($(CONFIG_SAM34_RTC),y)
CHIP_CSRCS += sam_rtc.c
endif

ifeq ($(CONFIG_SAM34_RTT),y)
CHIP_CSRCS += sam_rtt.c
endif

ifeq ($(CONFIG_SAM34_WDT),y)
CHIP_CSRCS += sam_wdt.c
endif

ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += sam_tc.c
endif

ifeq ($(CONFIG_ARCH_CHIP_SAM4CM),y)
ifeq ($(CONFIG_SAM34_TC),y)
CHIP_CSRCS += sam4cm_tc.c

ifeq ($(CONFIG_SAM34_ONESHOT),y)
CHIP_CSRCS += sam4cm_oneshot.c sam4cm_oneshot_lowerhalf.c
endif # CONFIG_SAM34_ONESHOT

ifeq ($(CONFIG_SAM34_FREERUN),y)
CHIP_CSRCS += sam4cm_freerun.c
endif # CONFIG_SAM34_FREERUN

ifeq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam4cm_tickless.c
endif # CONFIG_SCHED_TICKLESS
endif # CONFIG_SAM34_TC

ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += sam4cm_cpuindex.c sam4cm_cpuidlestack.c
CHIP_CSRCS += sam4cm_cpupause.c sam4cm_cpustart.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += sam4cm_idle.c
endif
endif # CONFIG_SMP

endif # CONFIG_ARCH_CHIP_SAM4CM