/**************************************************************************** * arch/arm/src/eoss3/eoss3_irq.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with * this work for additional information regarding copyright ownership. The * ASF licenses this file to you under the Apache License, Version 2.0 (the * "License"); you may not use this file except in compliance with the * License. You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the * License for the specific language governing permissions and limitations * under the License. * ****************************************************************************/ /**************************************************************************** * Included Files ****************************************************************************/ #include #include #include #include #include #include #include #include #include "nvic.h" #include "ram_vectors.h" #include "arm_arch.h" #include "sched/sched.h" #include "arm_internal.h" #include "chip.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ /* Get a 32-bit version of the default priority */ #define DEFPRIORITY32 \ (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ NVIC_SYSH_PRIORITY_DEFAULT) /* Given the address of a NVIC ENABLE register, this is the offset to * the corresponding CLEAR ENABLE register. */ #define NVIC_ENA_OFFSET (0) #define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) /**************************************************************************** * Public Data ****************************************************************************/ /* g_current_regs[] holds a references to the current interrupt level * register storage structure. If is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ volatile uint32_t *g_current_regs[1]; /* This is the address of the exception vector table (determined by the * linker script). */ extern uint32_t _vectors[]; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** * Name: eoss3_dumpnvic * * Description: * Dump some interesting NVIC registers * ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) static void eoss3_dumpnvic(const char *msg, int irq) { irqstate_t flags; flags = enter_critical_section(); irqinfo("NVIC (%s, irq=%d):\n", msg, irq); irqinfo(" INTCTRL: %08x VECTAB: %08x\n", getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x " "SYSTICK: %08x\n", getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); irqinfo(" IRQ ENABLE: %08x %08x %08x\n", getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE), getreg32(NVIC_IRQ64_95_ENABLE)); irqinfo(" SYSH_PRIO: %08x %08x %08x\n", getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), getreg32(NVIC_SYSH12_15_PRIORITY)); irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); irqinfo(" %08x %08x %08x %08x\n", getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); leave_critical_section(flags); } #else # define eoss3_dumpnvic(msg, irq) #endif /**************************************************************************** * Name: eoss3_nmi, eoss3_busfault, eoss3_usagefault, eoss3_pendsv, * eoss3_dbgmonitor, eoss3_pendsv, eoss3_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal * error conditions. The only advantage these provided over the default * unexpected interrupt handler is that they provide a diagnostic output. * ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES static int eoss3_nmi(int irq, FAR void *context, FAR void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); PANIC(); return 0; } static int eoss3_busfault(int irq, FAR void *context, FAR void *arg) { up_irq_save(); _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } static int eoss3_usagefault(int irq, FAR void *context, FAR void *arg) { up_irq_save(); _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } static int eoss3_pendsv(int irq, FAR void *context, FAR void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } static int eoss3_dbgmonitor(int irq, FAR void *context, FAR void *arg) { up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); PANIC(); return 0; } static int eoss3_reserved(int irq, FAR void *context, FAR void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } #endif /**************************************************************************** * Name: eoss3_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed * internally even if support for prioritized interrupts is not enabled. * ****************************************************************************/ #ifdef CONFIG_ARMV7M_USEBASEPRI static inline void eoss3_prioritize_syscall(int priority) { uint32_t regval; /* SVCALL is system handler 11 */ regval = getreg32(NVIC_SYSH8_11_PRIORITY); regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); putreg32(regval, NVIC_SYSH8_11_PRIORITY); } #endif /**************************************************************************** * Name: eoss3_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or * disable the irq. * ****************************************************************************/ static int eoss3_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; DEBUGASSERT(irq >= EOSS3_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt or a second level GPIO interrupt */ if (irq >= EOSS3_IRQ_INTERRUPTS) { if (irq < EOSS3_IRQ_NVECTORS) { n = irq - EOSS3_IRQ_INTERRUPTS; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } else { return -EINVAL; /* Invalid interrupt */ } } /* Handle processor exceptions. Only a few can be disabled */ else { *regaddr = NVIC_SYSHCON; if (irq == EOSS3_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } else if (irq == EOSS3_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } else if (irq == EOSS3_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } else if (irq == EOSS3_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; } else { return -EINVAL; /* Invalid or unsupported exception */ } } return OK; } /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** * Name: up_irqinitialize ****************************************************************************/ void up_irqinitialize(void) { uint32_t regaddr; int num_priority_registers; int i; /* Disable all interrupts */ for (i = 0; i < EOSS3_IRQ_NVECTORS - EOSS3_IRQ_INTERRUPTS; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } /* Make sure that we are using the correct vector table. The default * vector address is 0x0000:0000 but if we are executing code that is * positioned in SRAM or in external FLASH, then we may need to reset * the interrupt vector so that it refers to the table in SRAM or in * external FLASH. */ putreg32((uint32_t)_vectors, NVIC_VECTAB); #ifdef CONFIG_ARCH_RAMVECTORS /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based * vector table that requires special initialization. */ arm_ramvec_initialize(); #endif /* Set all interrupts (and exceptions) to the default priority */ putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); /* The NVIC ICTR register (bits 0-4) holds the number of interrupt * lines that the NVIC supports: * * 0 -> 32 interrupt lines, 8 priority registers * 1 -> 64 " " " ", 16 priority registers * 2 -> 96 " " " ", 32 priority registers * ... */ num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; /* Now set all of the interrupt lines to the default priority */ regaddr = NVIC_IRQ0_3_PRIORITY; while (num_priority_registers--) { putreg32(DEFPRIORITY32, regaddr); regaddr += 4; } /* currents_regs is non-NULL only while processing an interrupt */ CURRENT_REGS = NULL; /* Attach the SVCall and Hard Fault exception handlers. The SVCall * exception is used for performing context switches; The Hard Fault * must also be caught because a SVCall may show up as a Hard Fault * under certain conditions. */ irq_attach(EOSS3_IRQ_SVCALL, arm_svcall, NULL); irq_attach(EOSS3_IRQ_HARDFAULT, arm_hardfault, NULL); #ifdef CONFIG_ARMV7M_USEBASEPRI /* Set the priority of the SVCall interrupt */ eoss3_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); #endif /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. */ #ifdef CONFIG_ARM_MPU irq_attach(EOSS3_IRQ_MEMFAULT, arm_memfault, NULL); up_enable_irq(EOSS3_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES irq_attach(EOSS3_IRQ_NMI, eoss3_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(EOSS3_IRQ_MEMFAULT, arm_memfault, NULL); #endif irq_attach(EOSS3_IRQ_BUSFAULT, eoss3_busfault, NULL); irq_attach(EOSS3_IRQ_USAGEFAULT, eoss3_usagefault, NULL); irq_attach(EOSS3_IRQ_PENDSV, eoss3_pendsv, NULL); irq_attach(EOSS3_IRQ_DBGMONITOR, eoss3_dbgmonitor, NULL); irq_attach(EOSS3_IRQ_RESERVED, eoss3_reserved, NULL); #endif eoss3_dumpnvic("initial", EOSS3_IRQ_NVECTORS); #ifndef CONFIG_SUPPRESS_INTERRUPTS #ifdef CONFIG_EOSS3_GPIO_IRQ /* Initialize logic to support a second level of interrupt decoding for * GPIO pins. */ eoss3_gpioirqinitialize(); #endif /* And finally, enable interrupts */ up_irq_enable(); #endif } /**************************************************************************** * Name: up_disable_irq * * Description: * Disable the IRQ specified by 'irq' * ****************************************************************************/ void up_disable_irq(int irq) { uintptr_t regaddr; uint32_t regval; uint32_t bit; if (eoss3_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated * Interrupt Clear Enable register. For other exceptions, we need to * clear the bit in the System Handler Control and State Register. */ if (irq >= EOSS3_IRQ_INTERRUPTS) { putreg32(bit, regaddr); } else { regval = getreg32(regaddr); regval &= ~bit; putreg32(regval, regaddr); } } #ifdef CONFIG_EOSS3_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ eoss3_gpioirqdisable(irq); } #endif eoss3_dumpnvic("disable", irq); } /**************************************************************************** * Name: up_enable_irq * * Description: * Enable the IRQ specified by 'irq' * ****************************************************************************/ void up_enable_irq(int irq) { uintptr_t regaddr; uint32_t regval; uint32_t bit; if (eoss3_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated * Interrupt Set Enable register. For other exceptions, we need to * set the bit in the System Handler Control and State Register. */ if (irq >= EOSS3_IRQ_INTERRUPTS) { putreg32(bit, regaddr); } else { regval = getreg32(regaddr); regval |= bit; putreg32(regval, regaddr); } } #ifdef CONFIG_EOSS3_GPIO_IRQ else { /* Maybe it is a (derived) PIO IRQ */ eoss3_gpioirqenable(irq); } #endif eoss3_dumpnvic("enable", irq); } /**************************************************************************** * Name: arm_ack_irq * * Description: * Acknowledge the IRQ * ****************************************************************************/ void arm_ack_irq(int irq) { } /**************************************************************************** * Name: up_prioritize_irq * * Description: * Set the priority of an IRQ. * * Since this API is not supported on all architectures, it should be * avoided in common implementations where possible. * ****************************************************************************/ #ifdef CONFIG_ARCH_IRQPRIO int up_prioritize_irq(int irq, int priority) { uint32_t regaddr; uint32_t regval; int shift; DEBUGASSERT(irq >= EOSS3_IRQ_MEMFAULT && irq < EOSS3_IRQ_NVECTORS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); if (irq < EOSS3_IRQ_INTERRUPTS) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) */ regaddr = NVIC_SYSH_PRIORITY(irq); irq -= 4; } else (irq < EOSS3_IRQ_NVECTORS) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ irq -= EOSS3_IRQ_INTERRUPTS; regaddr = NVIC_IRQ_PRIORITY(irq); } else { /* Must be a GPIO interrupt */ return -EINVAL; } regval = getreg32(regaddr); shift = ((irq & 3) << 3); regval &= ~(0xff << shift); regval |= (priority << shift); putreg32(regval, regaddr); eoss3_dumpnvic("prioritize", irq); return OK; } #endif