303 lines
13 KiB
C
303 lines
13 KiB
C
/****************************************************************************
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* arch/z80/include/ez80/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h (via arch/irq.h)
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*/
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#ifndef __ARCH_Z80_INCLUDE_EZ80_IRQ_H
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#define __ARCH_Z80_INCLUDE_EZ80_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* ez80 Interrupt Numbers ***************************************************/
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#if defined(CONFIG_ARCH_CHIP_EZ80F91)
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# define EZ80_EMACRX_IRQ (0) /* Vector 0x40 */
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# define EZ80_EMACTX_IRQ (1) /* Vector 0x44 */
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# define EZ80_EMACSYS_IRQ (2) /* Vector 0x48 */
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# define EZ80_PLL_IRQ (3) /* Vector 0x4c */
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# define EZ80_FLASH_IRQ (4) /* Vector 0x50 */
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# define EZ80_TIMER0_IRQ (5) /* Vector 0x54 */
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# define EZ80_TIMER1_IRQ (6) /* Vector 0x58 */
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# define EZ80_TIMER2_IRQ (7) /* Vector 0x5c */
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# define EZ80_TIMER3_IRQ (8) /* Vector 0x60 */
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# define EZ80_RTC_IRQ (9) /* Vector 0x6C */
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# define EZ80_UART0_IRQ (10) /* Vector 0x70 */
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# define EZ80_UART1_IRQ (11) /* Vector 0x74 */
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# define EZ80_I2C_IRQ (12) /* Vector 0x78 */
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# define EZ80_SPI_IRQ (13) /* Vector 0x7c */
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# define EZ80_PORTA0_IRQ (14) /* Vector 0x80 */
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# define EZ80_PORTA1_IRQ (15) /* Vector 0x84 */
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# define EZ80_PORTA2_IRQ (16) /* Vector 0x88 */
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# define EZ80_PORTA3_IRQ (17) /* Vector 0x8c */
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# define EZ80_PORTA4_IRQ (18) /* Vector 0x90 */
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# define EZ80_PORTA5_IRQ (19) /* Vector 0x94 */
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# define EZ80_PORTA6_IRQ (20) /* Vector 0x98 */
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# define EZ80_PORTA7_IRQ (21) /* Vector 0x9c */
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# define EZ80_PORTB0_IRQ (22) /* Vector 0xa0 */
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# define EZ80_PORTB1_IRQ (23) /* Vector 0xa4 */
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# define EZ80_PORTB2_IRQ (24) /* Vector 0xa8 */
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# define EZ80_PORTB3_IRQ (25) /* Vector 0xac */
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# define EZ80_PORTB4_IRQ (26) /* Vector 0xb0 */
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# define EZ80_PORTB5_IRQ (27) /* Vector 0xb4 */
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# define EZ80_PORTB6_IRQ (28) /* Vector 0xb8 */
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# define EZ80_PORTB7_IRQ (29) /* Vector 0xbc */
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# define EZ80_PORTC0_IRQ (30) /* Vector 0xc0 */
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# define EZ80_PORTC1_IRQ (31) /* Vector 0xc4 */
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# define EZ80_PORTC2_IRQ (32) /* Vector 0xc8 */
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# define EZ80_PORTC3_IRQ (33) /* Vector 0xcc */
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# define EZ80_PORTC4_IRQ (34) /* Vector 0xd0 */
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# define EZ80_PORTC5_IRQ (35) /* Vector 0xd4 */
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# define EZ80_PORTC6_IRQ (36) /* Vector 0xd8 */
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# define EZ80_PORTC7_IRQ (37) /* Vector 0xdc */
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# define EZ80_PORTD0_IRQ (38) /* Vector 0xe0 */
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# define EZ80_PORTD1_IRQ (39) /* Vector 0xe4 */
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# define EZ80_PORTD2_IRQ (40) /* Vector 0xe8 */
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# define EZ80_PORTD3_IRQ (41) /* Vector 0xec */
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# define EZ80_PORTD4_IRQ (42) /* Vector 0xf0 */
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# define EZ80_PORTD5_IRQ (43) /* Vector 0xf4 */
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# define EZ80_PORTD6_IRQ (44) /* Vector 0xf8 */
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# define EZ80_PORTD7_IRQ (45) /* Vector 0xfc */
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# define NR_IRQS (46)
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#elif defined(CONFIG_ARCH_CHIP_EZ80F92) || defined(CONFIG_ARCH_CHIP_EZ80F93)
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# /* Vectors 0x00-0x06 unused */
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# define EZ80_FLASH_IRQ (0) /* Vector 0x08 */
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# define EZ80_TIMER0_IRQ (1) /* Vector 0x0a */
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# define EZ80_TIMER1_IRQ (2) /* Vector 0x0c */
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# define EZ80_TIMER2_IRQ (3) /* Vector 0x0e */
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# define EZ80_TIMER3_IRQ (4) /* Vector 0x10 */
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# define EZ80_TIMER4_IRQ (5) /* Vector 0x12 */
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# define EZ80_TIMER5_IRQ (6) /* Vector 0x14 */
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# define EZ80_RTC_IRQ (7) /* Vector 0x16 */
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# define EZ80_UART0_IRQ (8) /* Vector 0x18 */
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# define EZ80_UART1_IRQ (9) /* Vector 0x1a */
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# define EZ80_I2C_IRQ (10) /* Vector 0x1c */
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# define EZ80_SPI_IRQ (11) /* Vector 0x1e */
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# /* Vectors 0x20-0x2e unused */
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# define EZ80_PORTB0_IRQ (12) /* Vector 0x30 */
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# define EZ80_PORTB1_IRQ (13) /* Vector 0x32 */
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# define EZ80_PORTB2_IRQ (14) /* Vector 0x34 */
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# define EZ80_PORTB3_IRQ (15) /* Vector 0x36 */
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# define EZ80_PORTB4_IRQ (16) /* Vector 0x38 */
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# define EZ80_PORTB5_IRQ (17) /* Vector 0x3a */
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# define EZ80_PORTB6_IRQ (18) /* Vector 0x3c */
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# define EZ80_PORTB7_IRQ (19) /* Vector 0x3e */
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# define EZ80_PORTC0_IRQ (20) /* Vector 0x40 */
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# define EZ80_PORTC1_IRQ (21) /* Vector 0x42 */
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# define EZ80_PORTC2_IRQ (22) /* Vector 0x44 */
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# define EZ80_PORTC3_IRQ (23) /* Vector 0x46 */
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# define EZ80_PORTC4_IRQ (24) /* Vector 0x48 */
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# define EZ80_PORTC5_IRQ (25) /* Vector 0x4a */
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# define EZ80_PORTC6_IRQ (26) /* Vector 0x4c */
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# define EZ80_PORTC7_IRQ (27) /* Vector 0x4e */
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# define EZ80_PORTD0_IRQ (28) /* Vector 0x50 */
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# define EZ80_PORTD1_IRQ (29) /* Vector 0x52 */
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# define EZ80_PORTD2_IRQ (30) /* Vector 0x54 */
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# define EZ80_PORTD3_IRQ (31) /* Vector 0x56 */
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# define EZ80_PORTD4_IRQ (32) /* Vector 0x58 */
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# define EZ80_PORTD5_IRQ (33) /* Vector 0x5a */
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# define EZ80_PORTD6_IRQ (34) /* Vector 0x5c */
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# define EZ80_PORTD7_IRQ (35) /* Vector 0x5e */
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# /* Vectors 0x60-0x66 unused */
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# define NR_IRQS (36)
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#endif
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#define EZ80_IRQ_SYSTIMER EZ80_TIMER0_IRQ
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/* IRQ Management Macros ****************************************************/
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/* IRQ State Save Format ****************************************************
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*
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* These indices describe how the ez8 context is save in the state save array
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*
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* Byte offsets:
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*/
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/* IRQ Stack Frame Format
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*
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* This stack frame is created on each interrupt. These registers are stored
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* in the TCB to many context switches.
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*/
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/* chipreg_t indices */
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#define XCPT_I (0) /* Index 0: 16-bit interrupt vector register */
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#define XCPT_BC (1) /* Index 1: Saved 16-bit BC register */
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#define XCPT_DE (2) /* Index 2: Saved 16-bit DE register */
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#define XCPT_IX (3) /* Index 3: Saved 16-bit IX register */
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#define XCPT_IY (4) /* Index 4: Saved 16-bit IY register */
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#define XCPT_SP (5) /* Index 5: Saved 16-bit SP at time of interrupt */
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#define XCPT_HL (6) /* Index 6: Saved 16-bit HL register */
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#define XCPT_AF (7) /* Index 7: Saved 16-bit AF register */
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#define XCPT_PC (8) /* Index 8: Offset to 16-bit PC at time of interrupt */
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#define XCPTCONTEXT_REGS (9)
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#ifdef CONFIG_EZ80_Z80MODE
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/* Byte offsets */
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# define XCPT_I_OFFSET (2*XCPT_I) /* Offset 0: 16-bit interrupt vector register */
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# define XCPT_IF_OFFSET (2*XCPT_I+0) /* Offset 1: Saved flags. P set if interrupts enabled */
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# define XCPT_IA_OFFSET (2*XCPT_I+1) /* Offset 2: Saved lower 8-bits of interrupt vector register */
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# define XCPT_BC_OFFSET (2*XCPT_BC) /* Offset 2: Saved 16-bit BC register */
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# define XCPT_C_OFFSET (2*XCPT_BC+0) /* Offset 2: Saved 8-bit C register */
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# define XCPT_B_OFFSET (2*XCPT_BC+1) /* Offset 3: Saved 8-bit D register */
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# define XCPT_DE_OFFSET (2*XCPT_DE) /* Offset 4: Saved 16-bit DE register */
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# define XCPT_E_OFFSET (2*XCPT_DE+0) /* Offset 4: Saved 8-bit E register */
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# define XCPT_D_OFFSET (2*XCPT_DE+1) /* Offset 5: Saved 8-bit D register */
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# define XCPT_IX_OFFSET (2*XCPT_IX) /* Offset 6: Saved 16-bit IX register */
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# define XCPT_IY_OFFSET (2*XCPT_IY) /* Offset 8: Saved 16-bit IY register */
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# define XCPT_SP_OFFSET (2*XCPT_SP) /* Offset 10: Saved 16-bit SP at time of interrupt */
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# define XCPT_HL_OFFSET (2*XCPT_HL) /* Offset 12: Saved 16-bit HL register */
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# define XCPT_L_OFFSET (2*XCPT_HL+0) /* Offset 12: Saved 8-bit L register */
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# define XCPT_H_OFFSET (2*XCPT_HL+1) /* Offset 13: Saved 8-bit H register */
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# define XCPT_AF_OFFSET (2*XCPT_AF) /* Offset 14: Saved 16-bit AF register */
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# define XCPT_F_OFFSET (2*XCPT_AF+0) /* Offset 14: Saved flags */
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# define XCPT_A_OFFSET (2*XCPT_AF+1) /* Offset 15: Saved 8-bit A register */
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# define XCPT_PC_OFFSET (2*XCPT_PC) /* Offset 16: Offset to 16-bit PC at time of interrupt */
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# define XCPTCONTEXT_SIZE (2*XCPTCONTEXT_REGS)
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#else
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/* Byte offsets */
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# define XCPT_I_OFFSET (3*XCPT_I) /* Offset 0: Saved 24-bit interrupt vector register */
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# define XCPT_IF_OFFSET (3*XCPT_I+0) /* Offset 0: Saved flags. P set if interrupts enabled */
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# define XCPT_IA_OFFSET (3*XCPT_I+1) /* Offset 1: Saved lower 8-bits of interrupt vector register */
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# define XCPT_BC_OFFSET (3*XCPT_BC) /* Offset 3: Saved 24-bit BC register */
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# define XCPT_C_OFFSET (3*XCPT_BC+0) /* Offset 3: Saved 8-bit C register */
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# define XCPT_B_OFFSET (3*XCPT_BC+1) /* Offset 4: Saved 8-bit B register */
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# define XCPT_DE_OFFSET (3*XCPT_DE) /* Offset 6: Saved 24-bit DE register */
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# define XCPT_E_OFFSET (3*XCPT_DE+0) /* Offset 6: Saved 8-bit E register */
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# define XCPT_D_OFFSET (3*XCPT_DE+1) /* Offset 7: Saved 8-bit D register */
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# define XCPT_IX_OFFSET (3*XCPT_IX) /* Offset 9: Saved 24-bit IX register */
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# define XCPT_IY_OFFSET (3*XCPT_IY) /* Offset 12: Saved 24-bit IY register */
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# define XCPT_SP_OFFSET (3*XCPT_SP) /* Offset 15: Saved 24-bit SP at time of interrupt */
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# define XCPT_HL_OFFSET (3*XCPT_HL) /* Offset 18: Saved 24-bit HL register */
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# define XCPT_L_OFFSET (3*XCPT_HL+0) /* Offset 18: Saved 8-bit L register */
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# define XCPT_H_OFFSET (3*XCPT_HL+1) /* Offset 19: Saved 8-bit H register */
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# define XCPT_AF_OFFSET (3*XCPT_AF) /* Offset 21: Saved AF register */
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# define XCPT_F_OFFSET (3*XCPT_AF+0) /* Offset 21: Saved AF register */
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# define XCPT_A_OFFSET (3*XCPT_AF+1) /* Offset 22: Saved 8-bit A register */
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# define XCPT_PC_OFFSET (3*XCPT_PC) /* Offset 24: Offset to 24-bit PC at time of interrupt */
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# define XCPTCONTEXT_SIZE (3*XCPTCONTEXT_REGS)
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* This is the type of the register save array */
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#ifdef CONFIG_EZ80_Z80MODE
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typedef uint16_t chipreg_t;
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#else
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typedef uint24_t chipreg_t;
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#endif
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/* This struct defines the way the registers are stored. */
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struct xcptcontext
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{
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/* Register save area */
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chipreg_t regs[XCPTCONTEXT_REGS];
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/* The following retains that state during signal execution
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*
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* REVISIT: Because there is only one copy of these save areas,
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* only a single signal handler can be active. This precludes
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* queuing of signal actions. As a result, signals received while
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* another signal handler is executing will be ignored!
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*/
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chipreg_t saved_pc; /* Saved return address */
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chipreg_t saved_i; /* Saved interrupt state */
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};
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/* Name: up_irq_save, up_irq_restore, and friends.
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*
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* NOTE: These functions should never be called from application code and,
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* as a general rule unless you really know what you are doing, this
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* function should not be called directly from operation system code either:
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* Typically, the wrapper functions, enter_critical_section() and
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* leave_critical section(), are probably what you really want.
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*/
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irqstate_t up_irq_save(void);
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void up_irq_restore(irqstate_t flags);
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irqstate_t up_irq_enable(void);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_Z80_INCLUDE_EZ80_IRQ_H */
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