221 lines
8.1 KiB
C
221 lines
8.1 KiB
C
/****************************************************************************
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* arch/arm/src/lpc17xx/lpc17_clockconfig.c
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* arch/arm/src/chip/lpc17_clockconfig.c
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*
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* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "lpc17_clockconfig.h"
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#include "chip/lpc17_syscon.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef LPC176x
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# error "The logic in this file applies only to the LPC176x family"
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/************************************************************************************
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* Name: lpc17_clockconfig
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*
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* Description:
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* Called to initialize the LPC176x. This does whatever setup is needed to put the
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* SoC in a usable state. This includes the initialization of clocking using the
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* settings in board.h.
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*
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* The LPC176x and LPC178x system control block is *nearly* identical but we have
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* found that the LPC178x is more sensitive to the ordering of certain operations.
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* So, although the hardware seems very similar, the safer thing to do is to
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* separate the LPC176x and LPC178x into separate files.
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*
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************************************************************************************/
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void lpc17_clockconfig(void)
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{
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/* Enable the main oscillator (or not) and the frequency range of the main oscillator */
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putreg32(BOARD_SCS_VALUE, LPC17_SYSCON_SCS);
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/* Wait for the main oscillator to be ready. */
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#ifdef CONFIG_LPC17_MAINOSC
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while ((getreg32(LPC17_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0);
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#endif
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/* Setup up the divider value for the CPU clock. The output of the divider is CCLK.
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* The input to the divider (PLLCLK) is equal to SYSCLK unless PLL0 is enabled. CCLK
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* will be further divided to produce peripheral clocks, but that peripheral clock
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* setup is performed in the peripheral device drivers. Here only CCLK is
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* configured.
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*/
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putreg32(BOARD_CCLKCFG_VALUE, LPC17_SYSCON_CCLKCFG);
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/* PLL0 is used to generate the CPU clock divider input (PLLCLK). */
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#ifdef CONFIG_LPC17_PLL0
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/* Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that
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* a special "feed" sequence must be written to the PLL0FEED register in order
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* for changes to the PLL0CFG register to take effect.
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*/
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putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_SYSCON_CLKSRCSEL);
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putreg32(BOARD_PLL0CFG_VALUE, LPC17_SYSCON_PLL0CFG);
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putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_SYSCON_PLL0FEED);
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/* Enable the PLL. NOTE that a special "feed" sequence must be written to the
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* PLL0FEED register in order for changes to the PLL0CON register to take effect.
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*/
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putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL0CON);
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putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_SYSCON_PLL0FEED);
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/* Wait for PLL0 to lock */
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while ((getreg32(LPC17_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0);
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/* Enable and connect PLL0 */
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putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON);
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putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_SYSCON_PLL0FEED);
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/* Wait for PLL to report that it is connected and enabled */
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while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE | SYSCON_PLL0STAT_PLLC))
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!= (SYSCON_PLL0STAT_PLLE | SYSCON_PLL0STAT_PLLC));
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#endif /* CONFIG_LPC17_PLL0 */
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/* PLL1 receives its clock input from the main oscillator only and can be used to
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* provide a fixed 48 MHz clock only to the USB subsystem (if that clock cannot be
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* obtained from PLL0).
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*/
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#ifdef CONFIG_LPC17_PLL1
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/* Select the PLL1 multiplier, and pre-divider values. NOTE that a special "feed"
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* sequence must be written to the PLL1FEED register in order for changes to the
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* PLL1CFG register to take effect.
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*/
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putreg32(BOARD_PLL1CFG_VALUE, LPC17_SYSCON_PLL1CFG);
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putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_SYSCON_PLL1FEED);
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/* Enable the PLL. NOTE that a special "feed" sequence must be written to the
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* PLL1FEED register in order for changes to the PLL1CON register to take effect.
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*/
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putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL1CON);
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putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_SYSCON_PLL1FEED);
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/* Wait for PLL1 to lock */
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while ((getreg32(LPC17_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0);
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/* Enable and connect PLL1 */
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putreg32(SYSCON_PLLCON_PLLE | SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON);
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putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_SYSCON_PLL1FEED);
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/* Wait for PLL to report that it is connected and enabled */
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while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE | SYSCON_PLL1STAT_PLLC))
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!= (SYSCON_PLL1STAT_PLLE | SYSCON_PLL1STAT_PLLC));
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#else /* CONFIG_LPC17_PLL1 */
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/* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */
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putreg32(BOARD_USBCLKCFG_VALUE, LPC17_SYSCON_USBCLKCFG);
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#endif /* CONFIG_LPC17_PLL1 */
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/* Disable all peripheral clocks. They must be configured by each device driver
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* when the device driver is initialized.
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*/
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putreg32(0, LPC17_SYSCON_PCLKSEL0);
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putreg32(0, LPC17_SYSCON_PCLKSEL1);
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/* Disable power to all peripherals (execpt GPIO). Peripherals must be re-powered
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* one at a time by each device driver when the driver is initialized.
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*/
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putreg32(SYSCON_PCONP_PCGPIO, LPC17_SYSCON_PCONP);
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/* Disable CLKOUT */
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putreg32(0, LPC17_SYSCON_CLKOUTCFG);
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/* Configure FLASH */
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#ifdef CONFIG_LPC17_FLASH
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putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG);
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#endif
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}
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