005133323f
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4100 42af7a65-404d-4744-a932-0658087f49c3
122 lines
5.6 KiB
C
122 lines
5.6 KiB
C
/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_exti.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#if defined(CONFIG_STM32_STM32F10XX)
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# ifdef CONFIG_STM32_CONNECTIVITYLINE
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# define STM32_NEXTI 20
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# define STM32_EXTI_MASK 0x000fffff
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# else
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# define STM32_NEXTI 19
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# define STM32_EXTI_MASK 0x0007ffff
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# endif
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#elif defined(CONFIG_STM32_STM32F40XX)
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# define STM32_NEXTI 23
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# define STM32_EXTI_MASK 0x007fffff
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#endif
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#define STM32_EXTI_BIT(n) (1 << (n))
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/* Register Offsets *****************************************************************/
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#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */
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#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */
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#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */
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#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */
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#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */
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#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */
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/* Register Addresses ***************************************************************/
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#define STM32_EXTI_IMR (STM32_EXTI_BASE+STM32_EXTI_IMR_OFFSET)
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#define STM32_EXTI_EMR (STM32_EXTI_BASE+STM32_EXTI_EMR_OFFSET)
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#define STM32_EXTI_RTSR (STM32_EXTI_BASE+STM32_EXTI_RTSR_OFFSET)
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#define STM32_EXTI_FTSR (STM32_EXTI_BASE+STM32_EXTI_FTSR_OFFSET)
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#define STM32_EXTI_SWIER (STM32_EXTI_BASE+STM32_EXTI_SWIER_OFFSET)
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#define STM32_EXTI_PR (STM32_EXTI_BASE+STM32_EXTI_PR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* Interrupt mask register */
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#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
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#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
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#define EXTI_IMR_MASK STM32_EXTI_MASK
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/* Event mask register */
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#define EXTI_EMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Event request from line x is not mask */
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#define EXTI_EMR_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
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#define EXTI_EMR_MASK STM32_EXTI_MASK
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/* Rising Trigger selection register */
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#define EXTI_RTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
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#define EXTI_RTSR_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
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#define EXTI_RTSR_MASK STM32_EXTI_MASK
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/* Falling Trigger selection register */
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#define EXTI_FTSR_BIT(n) STM32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
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#define EXTI_FTSR_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
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#define EXTI_FTSR_MASK STM32_EXTI_MASK
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/* Software interrupt event register */
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#define EXTI_SWIER_BIT(n) STM32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
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#define EXTI_SWIER_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
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#define EXTI_SWIER_MASK STM32_EXTI_MASK
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/* Pending register */
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#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
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#define EXTI_IMR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_IMR_MASK STM32_EXTI_MASK
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H */
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