201 lines
6.6 KiB
Plaintext
201 lines
6.6 KiB
Plaintext
/****************************************************************************
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* boards/arm/stm32h7/nucleo-h743zi/scripts/flash.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* The STM32H743ZI has 2048Kb of main FLASH memory. The flash memory is
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* partitioned into a User Flash memory and a System Flash memory. Each
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* of these memories has two banks:
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*
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* 1) User Flash memory:
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*
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* Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each
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* Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each
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*
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* 2) System Flash memory:
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*
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* Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector
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* Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector
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*
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* 3) User option bytes for user configuration, only in Bank 1.
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*
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* In the STM32H743ZI, two different boot spaces can be selected through
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* the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
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* BOOT_ADD1 option bytes:
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*
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* 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
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* ST programmed value: Flash memory at 0x0800:0000
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* 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
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* ST programmed value: System bootloader at 0x1FF0:0000
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*
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* TODO: Check next paragraph with nucleo schematics
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*
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* NuttX does not modify these option bytes. On the unmodified NUCLEO-H743ZI
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* board, the BOOT0 pin is at ground so by default, the STM32 will boot
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* to address 0x0800:0000 in FLASH.
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*
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* The STM32H743ZI also has 1024Kb of data SRAM.
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* SRAM is split up into several blocks and into three power domains:
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*
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* 1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with
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* 0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus
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*
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* 1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000
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*
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* The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit
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* DTCM ports. The DTCM-RAM could be used for critical real-time
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* data, such as interrupt service routines or stack / heap memory.
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* Both DTCM-RAMs can be used in parallel (for load/store operations)
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* thanks to the Cortex-M7 dual issue capability.
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*
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* 1.2) 64Kb of ITCM-RAM beginning at address 0x0000:0000
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*
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* This RAM is connected to ITCM 64-bit interface designed for
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* execution of critical real-times routines by the CPU.
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*
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* 2) AXI SRAM (D1 domain) accessible by all system masters except BDMA
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* through D1 domain AXI bus matrix
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*
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* 2.1) 512Kb of SRAM beginning at address 0x2400:0000
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*
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* 3) AHB SRAM (D2 domain) accessible by all system masters except BDMA
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* through D2 domain AHB bus matrix
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*
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* 3.1) 128Kb of SRAM1 beginning at address 0x3000:0000
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* 3.2) 128Kb of SRAM2 beginning at address 0x3002:0000
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* 3.3) 32Kb of SRAM3 beginning at address 0x3004:0000
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*
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* SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000
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*
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* 4) AHB SRAM (D3 domain) accessible by most of system masters
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* through D3 domain AHB bus matrix
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*
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* 4.1) 64Kb of SRAM4 beginning at address 0x3800:0000
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* 4.1) 4Kb of backup RAM beginning at address 0x3880:0000
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*
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* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
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* where the code expects to begin execution by jumping to the entry point in
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* the 0x0800:0000 address range.
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*/
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MEMORY
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{
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itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
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flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
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dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
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dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K
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sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
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sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K
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sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K
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sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K
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sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
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bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
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}
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OUTPUT_ARCH(arm)
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EXTERN(_vectors)
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ENTRY(_stext)
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SECTIONS
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{
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.text :
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{
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_stext = ABSOLUTE(.);
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*(.vectors)
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*(.text .text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.rodata .rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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_etext = ABSOLUTE(.);
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} > flash
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.init_section :
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{
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_sinit = ABSOLUTE(.);
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*(.init_array .init_array.*)
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_einit = ABSOLUTE(.);
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} > flash
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.ARM.extab :
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{
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*(.ARM.extab*)
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} > flash
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__exidx_start = ABSOLUTE(.);
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.ARM.exidx :
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{
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*(.ARM.exidx*)
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} > flash
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__exidx_end = ABSOLUTE(.);
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_eronly = ABSOLUTE(.);
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.data :
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{
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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. = ALIGN(4);
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_edata = ABSOLUTE(.);
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} > sram AT > flash
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.bss :
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{
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_sbss = ABSOLUTE(.);
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*(.bss .bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = ABSOLUTE(.);
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} > sram
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/* Emit the the D3 power domain section for locating BDMA data
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*
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* Static data with locate_data(".sram4") will be located
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* at start of SRAM4; the rest of SRAM4 will be added to the heap.
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*/
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.sram4_reserve (NOLOAD) :
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{
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*(.sram4)
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. = ALIGN(4);
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_sram4_heap_start = ABSOLUTE(.);
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} > sram4
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_info 0 : { *(.debug_info) }
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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}
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