9998f85110
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2359 42af7a65-404d-4744-a932-0658087f49c3
82 lines
5.0 KiB
C
82 lines
5.0 KiB
C
/************************************************************************************
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* dm320/dm320_clkc.h
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*
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* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_DM320_DM320_CLKC_H
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#define __ARCH_ARM_SRC_DM320_DM320_CLKC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clock Controller Register Map (CLKC) *********************************************/
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#define DM320_CLKC_PLLA (DM320_CLKC_REGISTER_BASE+0x0000) /* PLLA Configuration */
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#define DM320_CLKC_PLLB (DM320_CLKC_REGISTER_BASE+0x0002) /* PLLB Configuration */
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#define DM320_CLKC_SEL0 (DM320_CLKC_REGISTER_BASE+0x0004) /* Input Clock Source Selection #0 */
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#define DM320_CLKC_SEL1 (DM320_CLKC_REGISTER_BASE+0x0006) /* Input Slock Source Selection #1 */
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#define DM320_CLKC_SEL2 (DM320_CLKC_REGISTER_BASE+0x0008) /* Input Clock Source Selection #2 */
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#define DM320_CLKC_DIV0 (DM320_CLKC_REGISTER_BASE+0x000a) /* Clock Divisor Settings #0 */
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#define DM320_CLKC_DIV1 (DM320_CLKC_REGISTER_BASE+0x000c) /* Clock Divisor Settings #1 */
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#define DM320_CLKC_DIV2 (DM320_CLKC_REGISTER_BASE+0x000e) /* Clock Divisor Settings #2 */
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#define DM320_CLKC_DIV3 (DM320_CLKC_REGISTER_BASE+0x0010) /* Clock Divisor Settings #3 */
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#define DM320_CLKC_DIV4 (DM320_CLKC_REGISTER_BASE+0x0012) /* Clock Divisor Settings #4 */
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#define DM320_CLKC_BYP (DM320_CLKC_REGISTER_BASE+0x0014) /* Bypass Control */
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#define DM320_CLKC_INV (DM320_CLKC_REGISTER_BASE+0x0016) /* Inverse Control */
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#define DM320_CLKC_MOD0 (DM320_CLKC_REGISTER_BASE+0x0018) /* Module Clock Enables #0 */
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#define DM320_CLKC_MOD1 (DM320_CLKC_REGISTER_BASE+0x001a) /* Module ClockEnables #1 */
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#define DM320_CLKC_MOD2 (DM320_CLKC_REGISTER_BASE+0x001c) /* Module ClockEnables #1 */
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#define DM320_CLKC_LPCTL0 (DM320_CLKC_REGISTER_BASE+0x001e) /* Low Power Control #0 */
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#define DM320_CLKC_LPCTL1 (DM320_CLKC_REGISTER_BASE+0x0020) /* Low Power Control #1 */
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#define DM320_CLKC_OSEL (DM320_CLKC_REGISTER_BASE+0x0022) /* Output Clock Selector */
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#define DM320_CLKC_O0DIV (DM320_CLKC_REGISTER_BASE+0x0024) /* Output Clock #0 Divider */
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#define DM320_CLKC_O1DIV (DM320_CLKC_REGISTER_BASE+0x0026) /* Output Clock #1 Divider */
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#define DM320_CLKC_O2DIV (DM320_CLKC_REGISTER_BASE+0x0028) /* Output Clock #2 Divider */
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#define DM320_CLKC_PWM0C (DM320_CLKC_REGISTER_BASE+0x002a) /* PWM #0 Cycle Count */
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#define DM320_CLKC_PWM0H (DM320_CLKC_REGISTER_BASE+0x002c) /* PWM #0 High Period */
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#define DM320_CLKC_PWM1C (DM320_CLKC_REGISTER_BASE+0x002e) /* PWM #1 Cycle Count */
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#define DM320_CLKC_PWM1H (DM320_CLKC_REGISTER_BASE+0x0030) /* PWM #1 Cycle Period */
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#define DM320_CLKC_TEST0 (DM320_CLKC_REGISTER_BASE+0x08FE) /* Test #0 */
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#define DM320_CLKC_TEST1 (DM320_CLKC_REGISTER_BASE+0x08FE) /* Test #1 */
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_DM320_DM320_CLKC_H */
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