Huang Qi 00efcd3308 arch/risc-v: Merge riscv_getnewintctx into common ...

And also mask the bits which should be preserved (from ISA spec)

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>

2022-03-19 17:38:18 +08:00

..

include

arch/risc-v: Merge riscv_getnewintctx into common

2022-03-19 17:38:18 +08:00

src

arch/risc-v: Merge riscv_getnewintctx into common

2022-03-19 17:38:18 +08:00

Kconfig

arch/risc-v: Save/Load float register in setjmp

2022-03-09 10:15:54 +02:00