321 lines
13 KiB
ReStructuredText
321 lines
13 KiB
ReStructuredText
=============================
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Zynq UltraScale+ RFSoC ZCU111
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=============================
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The `ZCU111 <https://www.xilinx.com/products/boards-and-kits/zcu111.html>`_ is a
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development board based on the Zynq UltraScale+ RFSoC(XCZU28DR) from XilinX(AMD).
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Features
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========
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- **RF Data Converter**
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- **12-bit ADC:** 8, Max Rate 4.096G
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- **14-bit DAC:** 8, Max Rate 6.554G
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- **SD-FEC:** SD-FEC
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- **Memory**
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- **PS DDR4:** 4GB 64-bit SODIMM
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- **SD-Card:** Yes
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- **M.2 SATA Connector:** Yes
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- **QSPI:** 2
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- **Communications & Networking**
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- **USB UART/JTAG:** 1
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- **RJ45:** 1
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- **SFP+:** 4
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- **USB 3.0:** 1
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- **Expansion Connectors**
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- **FMC-HPC Connector:** 2
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- **PMOD:** 2
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- **RFMC 1.0:** 2
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- **QSPI:** 2
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- **Control & I/O**
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- **I2C:** Yes
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- **PMBUS:** Yes
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- **JTAG PC4 Header:** Yes
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- **Boot Options**
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- **ISD Boot:** Yes
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- **QSPI Boot:** Yes
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- **JTAG Boot:** Yes
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- **DDR4 SODIMM:** 4GB 64-bit, 2400MT/s, attached to Processor Subsystem (PS)
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Serial Console
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==============
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Serial console for the PS:
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===== ======== =============
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Pin Signal Notes
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===== ======== =============
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MIO18 UART0 TX USB UART COM0
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MIO19 UART0 RX USB UART COM0
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===== ======== =============
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PS-side UART interface and is connected to the FTDI U34 FT4232HL USB-to-Quad-UART
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bridge port B Connect ZCU111 to our computer with the USB Cable. On our computer
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start a Serial Terminal and connect to the USB Serial Port at **115200 bps**.
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NuttX will appear in the Serial Console when it boots on zcu111.
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LEDs and Buttons
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================
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The PS-side pushbutton SW19 is connected to MIO22 (pin U1.Y28). The PS-side LED DS50,
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which is physically placed adjacent to the pushbutton, is connected to MIO23(pin U1.U29).
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Configurations
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==============
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Each configuration is maintained in a sub-directory and can be selected as follow::
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tools/configure.sh zcu111:<subdir>
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Where <subdir> is one of the following:
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jtag
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----
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Basic NuttShell configuration for JTAG boot mode (nsh console enabled in UART0,
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UART and JTAG exposed via FT4232HL USB-to-Quad-UART bridge port and USB cable).
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nsh
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---
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Basic NuttShell configuration for Flash boot mode. We need create boot image with
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zynqmp_fsbl.elf, zynqmp_pmufw.elf, bl31.elf and nuttx.elf in Vivado SDK or XSCT
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shell. Also we need copy BOOT.BIN into SD Card(in SD card boot mode) or Flash it
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into the QSPI FLASH(in QSPI boot mode).
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ARM64 Toolchain
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===============
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There are two ways to install the toolchain for Zynq MPSoC:
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The first way is download the ARM64 Toolchain ``aarch64-none-elf`` from
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`Arm GNU Toolchain Downloads <https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads>`_.
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Add the downloaded toolchain ``gcc-arm-...-aarch64-none-elf/bin``
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to the ``PATH`` Environment Variable such as:
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.. code-block:: console
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$ echo "export PATH=/home/username/tools/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin:$PATH" >> ~/.profile
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You can edit your .profile files if you don't use bash.
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The second way is install Vivado SDK or Vitis development environment which included a complete
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``aarch64-none-elf`` toolchain and we also add it to the ``PATH`` Environment Variable such as:
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.. code-block:: console
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$ echo "export PATH=/home/username/tools/Xilinx/SDK/2018.3/gnu/aarch64/lin/aarch64-none/bin:$PATH" >> ~/.profile
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You can edit your .profile files if you don't use bash.
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Note: nuttx.elf build by toolchain install in first way can't be debuged by Vivado SDK which use
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toolchain of second way for gdb version incompatibility.
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Check the ARM64 Toolchain:
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.. code:: console
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$ aarch64-none-elf-gcc -v
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Building
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========
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There are two types of NuttX image for Zynq MPSoC: debug by JTAG and boot from FLASH.
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debug by jtag
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-------------
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We just configure the NuttX project and build the project:
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.. code:: console
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$ cd nuttx
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$ tools/configure.sh zcu111:jtag
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$ make
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Set the Project to nuttx and Application to nuttx.elf for psu_cortexa53_0 in Vivado SDK Debug Configuration.
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Just click Debug button then we can debug NuttX.
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boot from flash
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---------------
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To boot from FLASH, we have to create BOOT.BIN image and flash it into QSPI FLASH or SD card. To create BOOT.BIN
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in addition to building nuttx.elf, we also need to build zynqmp_fsbl.elf, zynqmp_pmufw.elf and bl31.elf
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To build nuttx.elf we just configure the NuttX project and build the project:
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.. code:: console
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$ cd nuttx
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$ tools/configure.sh zcu111:nsh
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$ make
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build bl31.elf
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--------------
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To build bl31.elf we should fetch Fetch sources of ARM Trusted Firmware (ATF) and checkout the tags that
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corresponding to the SDK version. Take Vivado 2018.3 for example:
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.. code:: console
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$ git clone https://github.com/Xilinx/arm-trusted-firmware.git
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$ cd arm-trusted-firmware
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$ git checkout xilinx-v2018.3
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By default, the Arm-trusted firmware builds for OCM space at address 0xFFFEA000, and ATF assume that UBoot
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or nuttx.elf located at address 0x08000000. Then we just build bl31.elf with:
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.. code:: console
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$ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1
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But, with DEBUG flag set to 1, it can't fit in OCM, so by default with DEBUG=1, it builds for DDR location
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0x1000 with build flag DEBUG=1 mentioned while building. Alternatively, user has always an option to build
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for the location of their choice by specifying the build flags ZYNQMP_ATF_MEM_BASE, ZYNQMP_ATF_MEM_SIZE while
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building. The flag ZYNQMP_ATF_MEM_BASE specifies the base address of ATF and flag ZYNQMP_ATF_MEM_SIZE specifies
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the maximum size the ATF image can be. what's more we can specifies the target address of Uboot or nuttx.elf
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by PRELOADED_BL33_BASE. for zcu111:nsh configuration Example bl31 build command:
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.. code:: console
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$ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 ZYNQMP_ATF_MEM_BASE=0x10000 ZYNQMP_ATF_MEM_SIZE=0x40000 PRELOADED_BL33_BASE=0x100000
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If we don't dubug bl31 we just build bl31 in following command:
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.. code:: console
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$ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 PRELOADED_BL33_BASE=0x100000
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After the build process completes the bl31.elf binary is created within the /build/zynqmp/release/bl31 directory.
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build zynqmp_pmufw.elf
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----------------------
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The Platform Management Unit (PMU) in Zynq MPSoC has a Microblaze with 32 KB of ROM and 128 KB of RAM. The ROM is
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pre-loaded with PMU Boot ROM (PBR) which performs pre-boot tasks and enters a service mode. For more details on PMU,
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PBR and PMUFW load sequence, refer to Platform Management Unit (Chapter-6) in Zynq MPSoC TRM (UG1085). PMU RAM can
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be loaded with a firmware (PMU Firmware) at run-time and can be used to extend or customize the functionality of PMU.
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Some part of the RAM is reserved for PBR, leaving around 125.7 KB for PMU Firmware.
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There are usually two flows to create and build a PMU Firmware image for the target, Xilinx Vitis or Vivado SDK IDE or
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hsi command line. The PMU Firmware is provided as a template application for the PMU processor for any hardware platform
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including the Zynq MPSoC device. The steps required to create and build it can be applied by selecting the appropriate
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platform, processor, and template to create zynqmp_pmufw.elf. We can also create PMU Firmware from system hardware
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project hdf file by hsi command line:
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.. code-block::
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proc generate_pmufw {} {
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if {[file exists pmu_fw/zynqmp_pmufw.elf] != 1} {
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set pmufw_design [hsi::create_sw_design pmu_1 -proc psu_pmu_0 -app zynqmp_pmufw]
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hsi::add_library libmetal
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hsi::generate_app -dir pmu_fw -compile
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return "pmu_fw/zynqmp_pmufw.elf"
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}
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return "pmu_fw/zynqmp_pmufw.elf"
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}
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In order to call this procs, the user needs to open the hdf (hsi::open_hw_design):
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.. code-block::
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proc create_pmufw {hdf} {
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hsi::open_hw_design $hdf
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set pmufw [generate_pmufw]
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hsi::close_hw_design [hsi::current_hw_design]
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}
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Create a TCL script with HSI commands above -> Create a TCL script with HSI commands above ->
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Launch XSCT 2018.3 -> Change directory to the zipped directory -> source xsct_script.tcl ->
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create_pmufw design_1_wrapper.hdf
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build zynqmp_fsbl.elf
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---------------------
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First Stage Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures the FPGA with hardware bitstream (if it exists)
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and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile
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memory (SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes A53/R5 out of reset. It supports multiple partitions, and each
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partition can be a code image or a bitstream. Each of these partitions, if required, will be authenticated and/or decrypted.
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FSBL is loaded into OCM and handed off by CSU BootROM after authenticating and/or decrypting (as required) FSBL.
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There are usually two flows to create and build a PMU Firmware image for the target, Xilinx Vitis or Vivado SDK IDE or
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hsi command line.
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To create FSBL by Vitis or Vivado SDK IDE just launch VITIS or Vivado SDK and do following flow:
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- Provide path where VITIS workspace and project need to be created. With this VITIS workspace will be created
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- (Optional step) To work with local repos, Select "Xilinx" (ALT - x) -> Repositories. Against Local Repositories,
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click on "New..." and provide path of the local repo
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- Select File-->New-->Application Project to open "New Project" window, provide name for FSBL project
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- In the “Platform” section, click on “Create a new platform from hardware (XSA)” and select pre-defined hardware platform for ZynqMP.
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- Alternatively, to create a new/custom platform from a .xsa file, click on “+”, browse and select the XSA file and a new hardware platform is created.
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- In the "Domain" window, select the processor psu_cortexa53_0/psu_cortexr5_0, OS as standalone and Language as C.
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- Click Next and select "Zynq MP FSBL"
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- Click "Finish" to generate the A53/R5 FSBL. This populates the FSBL code and also builds it (along with BSP)
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- Debug prints in FSBL are now disabled by default. To enable debug prints, define symbol: FSBL_DEBUG_INFO.
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- In VITIS this can be done by: right click on FSBL application project -> select “C/C++ Build Settings” -> “Tool Settings” tab -> Symbols (under ARM v8 gcc compiler)
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- Click on Add (+) icon and Enter Value: FSBL_DEBUG_INFO, click on "OK" to close the "Enter Value" screen
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- In case any of the source files (FSBL or BSP) need to be modified, browse the file, make the change and save the file,
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build the project. elf file will be present in the Debug/Release folder of FSBL project.
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To create FSBL by XSCT command line just launch XSCT console and execute following TCL script with HSI commands:
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.. code-block::
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proc generate_fsbl {} {
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if {[file exists zynqmp_fsbl/zynqmp_fsbl.elf] != 1} {
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set fsbl_design [hsi::create_sw_design fsbl_1 -proc psu_cortexa53_0 -app zynqmp_fsbl]
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common::set_property APP_COMPILER "aarch64-none-elf-gcc" $fsbl_design
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common::set_property -name APP_COMPILER_FLAGS -value "-DRSA_SUPPORT -DFSBL_DEBUG_INFO -DXPS_BOARD_ZCU111" -objects $fsbl_design
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hsi::add_library libmetal
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hsi::generate_app -dir zynqmp_fsbl -compile
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}
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return "zynqmp_fsbl/zynqmp_fsbl.elf"
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}
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In order to call this procs, the user needs to open the hdf (hsi::open_hw_design):
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.. code-block::
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proc create_fsbl {hdf} {
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hsi::open_hw_design $hdf
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set fsbl [generate_fsbl]
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hsi::close_hw_design [hsi::current_hw_design]
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}
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Create a TCL script with HSI commands above -> Create a TCL script with HSI commands above ->
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Launch XSCT 2018.3 -> Change directory to the zipped directory -> source xsct_script.tcl ->
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create_fsbl design_1_wrapper.hdf
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generate BOOT.bin image
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-----------------------
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You can create BOOT.bin images using the BIF attributes and the Bootgen command.
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For this configuration, the BIF file(named fsbl.bif) contains the following attributes:
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.. code-block::
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the_ROM_image:
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{
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[fsbl_config]a53_x64
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[bootloader]zynqmp_fsbl.elf
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[pmufw_image]zynqmp_pmufw.elf
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[destination_cpu = a53-0, exception_level = el-3, trustzone]bl31.elf
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[destination_cpu = a53-0, exception_level = el-1]nuttx.elf
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}
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The Vitis IDE calls the following Bootgen command to generate the BOOT.bin image for this configuration:
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.. code-block::
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bootgen -image fsbl.bif -arch zynqmp -o .\BOOT.bin
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Flash BOOT.bin to QSPI FLASH
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----------------------------
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We can flash BOOT.bin into QSPI FLASH in following flow:
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- In the Vivado SDK/Vitis IDE, select Xilinx -> Program Flash.
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- In the Program Flash wizard, browse to and select the BOOT.bin image file that was created as a part of this example.
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- Select **qspi-x8-dual_parallel** as the Flash type.
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- Set the Offset as 0 and select the BOOT.bin file.
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- Click Program to start the process of programming the QSPI flash with the BOOT.bin.
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- Wait until you see the message “Flash Operation Successful” in the console.
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Set mode switch SW6 to QSPI32, NuttX will appear in the Serial Console when we power on zcu111.
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