2192d83200
Add support for XSAVE/XRSTOR to handle x86_64 procesor extended states. Support for these instructions is required to support AVX instruction set Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
174 lines
4.3 KiB
Plaintext
174 lines
4.3 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_INTEL64
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comment "intel64 Configuration Options"
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choice
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prompt "Intel64 Chip Selection"
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default ARCH_CHIP_INTEL64_QEMU
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config ARCH_CHIP_INTEL64_QEMU
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bool "Intel64 QEMU"
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config ARCH_CHIP_INTEL64_CUSTOM
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bool "Custom Intel64 chip"
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endchoice # "Intel64 Chip Selection"
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config ARCH_INTEL64_HAVE_TSC
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bool
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config ARCH_INTEL64_CACHE_LINESIZE
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int "Cache line size (hardcoded)"
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depends on ARCH_DCACHE || ARCH_ICACHE
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default 64
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---help---
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Cache line size. If set to 0, we read the value from CPUID,
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(Probably) all new Intel CPUs have this value equal to 64.
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config ARCH_INTEL64_DCACHE_SIZE
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int "Data cache line size (L1d)"
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depends on ARCH_DCACHE
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default 0
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---help---
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Data cache line size (L1d). If set to 0, we read the value from CPUID.
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config ARCH_INTEL64_ICACHE_SIZE
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int "Instruction cache line size (L1i)"
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depends on ARCH_ICACHE
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default 0
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---help---
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Instruction cache line size (L1i). If set to 0, we read the value from CPUID.
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config ARCH_INTEL64_HAVE_CLWB
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bool "CLWB support"
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default n
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---help---
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Select to enable the use of CLWB to write back cache line
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choice
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prompt "System Timer Source"
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default ARCH_INTEL64_TSC_DEADLINE
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---help---
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Choose which hardware resource will drive NuttX
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system time
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config ARCH_INTEL64_TSC_DEADLINE
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bool "TSC DEADLINE timer support"
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select ARCH_INTEL64_HAVE_TSC
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---help---
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Select to enable the use of TSC DEADLINE timer of x86_64
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config ARCH_INTEL64_TSC
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bool "TSC APIC timer support"
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select ARCH_INTEL64_HAVE_TSC
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---help---
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Select to enable the use of TSC APIC timer of x86_64
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endchoice # System Timer Source
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if ARCH_INTEL64_TSC_DEADLINE
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config ARCH_INTEL64_CORE_FREQ_KHZ
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int "CPU Core frequency in kHz"
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default 2000000
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---help---
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The CPU Core frequency (without Turbo boost). This is used
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to set the TSC deadline timer frequency. If set to 0 we try to get
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frequency from CPUID.
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endif
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if ARCH_INTEL64_TSC
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config ARCH_INTEL64_APIC_FREQ_KHZ
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int "APIC timer frequency in kHz"
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default 2000000
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---help---
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The APIC timer frequency. This is used to set the APIC timer
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frequency in case of no TSC DEADLINE timer is available.
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endif
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config INTEL64_HPET
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bool "HPET timer support"
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default n
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---help---
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Select to enable the HPET timer support
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if INTEL64_HPET
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config INTEL64_HPET_BASE
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hex "HPET timer base address"
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default 0xfed00000
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---help---
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Configure base address for HPET. In the future, we can get this address from
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the ACPI table if ACPI support is enabled.
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config INTEL64_HPET_CHANNELS
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int "HPET timer supported channels"
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default 2
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range 1 3
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---help---
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Configure the number of supported HPET channles (called HPET timers
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in HPET spec). We use HPET legacy replacement for interrupts which
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means that Timer 0 and Timer 1 interrupts are hardcoded, but Timer 2
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needs additional attention to configure interrupt routing.
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Timer 2 will most likely not work with QEMU.
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config INTEL64_HPET_MIN_DELAY
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int "HPET minimum supported delay in micro-seconds"
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default 1000
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---help---
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HPET use free runnin up-counter and a comparators which generate events
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only on a equal event. This can results in event miss if we set too small
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delay. In that case we must set a minimum value for delay that always work.
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For the QEMU target this value should be as high as 1000, but for real
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hardware it may go much lower (for i7-1255U CPU it works with values <10).
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endif # INTEL64_HPET
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config INTEL64_ONESHOT
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bool "Oneshot timer support"
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select INTEL64_HPET
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default n
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---help---
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Select to enable the oneshot timer support
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if INTEL64_ONESHOT
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config INTEL64_ONESHOT_MAXTIMERS
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int "Maximum number of oneshot timers"
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default 1
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range 1 3
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---help---
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Determines the maximum number of oneshot timers that can be
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supported.
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endif
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config ARCH_INTEL64_HAVE_PCID
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bool "PCID support"
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default y
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---help---
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Select to enable the use of PCID to reduce TLB flush
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config ARCH_INTEL64_HAVE_RDRAND
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bool "RDRAND support"
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default y
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---help---
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Select to enable the use of RDRAND for /dev/random
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config ARCH_INTEL64_DISABLE_INT_INIT
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bool "Disable Initialization of 8259/APIC/IO-APIC"
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default n
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---help---
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Select to disable all initialization related to interrupt
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controllers. This is necessary if those are already
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initialized, i.e. Jailhouse system.
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endif
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