e5dfd805e6
Add support for LPC40xx family chips
* Corrected a few peripheral definitions and pin functions for the LPC17xx family.
Added configuration options, chip definitions, and additional pin functions for the LPC40xx family.
Added board configurations for Embedded Artists LPC4088 Quickstart board and LPC4088 Developer's kit. These configurations are still something of a work in progress. In particular, the LCD functionality is untested.
* First pass rename in *.c and *.h files.
* Renamed LPC17XX to LPC17XX_40XX in config files
* Rplaced LPC17xx with LPC17xx/LPC40xx in .c files
* Replaced LPC17xx with LPC17xx/LPC40xx in .h files
* Updated some documentation
* Working on moving directories
* moved arch/arm/src/lpc17xx and arch/arm/include/lpc17xx to lpc17xx_40xx
* Renamed LPC17_* constants / configuration options to LPC17_40_*
* Updated chip family name defines
* Renamed some chip-specific files
* Updated references to renamed files
* Updated references to lpc17_ to lpc17_40_
* Renamed source files from lpc17_* to lpc17_40_*
* Clean up white space
Approved-by: Gregory Nutt <gnutt@nuttx.org>
580 lines
17 KiB
C
580 lines
17 KiB
C
/****************************************************************************
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* arch/arm/src/lpc17/lpc17_40_irq.c
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*
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* Copyright (C) 2010-2011, 2013-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include <arch/armv7-m/nvicpri.h>
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#include "nvic.h"
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#include "ram_vectors.h"
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#include "up_arch.h"
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#include "up_internal.h"
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#include "lpc17_40_gpio.h"
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#include "lpc17_40_clrpend.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Get a 32-bit version of the default priority */
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#define DEFPRIORITY32 \
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(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
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NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
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NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
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NVIC_SYSH_PRIORITY_DEFAULT)
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/* Given the address of a NVIC ENABLE register, this is the offset to
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* the corresponding CLEAR ENABLE register.
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*/
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#define NVIC_ENA_OFFSET (0)
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#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* g_current_regs[] holds a references to the current interrupt level
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* register storage structure. If is non-NULL only during interrupt
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* processing. Access to g_current_regs[] must be through the macro
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* CURRENT_REGS for portability.
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*/
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volatile uint32_t *g_current_regs[1];
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/* This is the address of the exception vector table (determined by the
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* linker script).
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*/
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extern uint32_t _vectors[];
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc17_40_dumpnvic
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*
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* Description:
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* Dump some interesting NVIC registers
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*
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****************************************************************************/
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#if defined(CONFIG_DEBUG_IRQ_INFO)
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static void lpc17_40_dumpnvic(const char *msg, int irq)
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{
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irqstate_t flags;
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flags = enter_critical_section();
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irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
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irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
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getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
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#if 0
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irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
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getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
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getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
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#endif
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irqinfo(" IRQ ENABLE: %08x\n", getreg32(NVIC_IRQ0_31_ENABLE));
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irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
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getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
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getreg32(NVIC_SYSH12_15_PRIORITY));
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irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
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getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
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getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
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irqinfo(" %08x %08x %08x %08x\n",
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getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
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getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
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leave_critical_section(flags);
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}
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#else
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# define lpc17_40_dumpnvic(msg, irq)
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#endif
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/****************************************************************************
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* Name: lpc17_40_nmi, lpc17_40_busfault, lpc17_40_usagefault, lpc17_40_pendsv,
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* lpc17_40_dbgmonitor, lpc17_40_pendsv, lpc17_40_reserved
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*
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* Description:
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* Handlers for various execptions. None are handled and all are fatal
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* error conditions. The only advantage these provided over the default
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* unexpected interrupt handler is that they provide a diagnostic output.
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_FEATURES
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static int lpc17_40_nmi(int irq, FAR void *context, FAR void *arg)
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{
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(void)up_irq_save();
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_err("PANIC!!! NMI received\n");
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PANIC();
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return 0;
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}
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static int lpc17_40_busfault(int irq, FAR void *context, FAR void *arg)
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{
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(void)up_irq_save();
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_err("PANIC!!! Bus fault recived\n");
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PANIC();
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return 0;
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}
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static int lpc17_40_usagefault(int irq, FAR void *context, FAR void *arg)
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{
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(void)up_irq_save();
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_err("PANIC!!! Usage fault received\n");
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PANIC();
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return 0;
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}
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static int lpc17_40_pendsv(int irq, FAR void *context, FAR void *arg)
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{
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(void)up_irq_save();
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_err("PANIC!!! PendSV received\n");
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PANIC();
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return 0;
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}
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static int lpc17_40_dbgmonitor(int irq, FAR void *context, FAR void *arg)
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{
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(void)up_irq_save();
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_err("PANIC!!! Debug Monitor received\n");
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PANIC();
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return 0;
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}
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static int lpc17_40_reserved(int irq, FAR void *context, FAR void *arg)
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{
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(void)up_irq_save();
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_err("PANIC!!! Reserved interrupt\n");
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PANIC();
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return 0;
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}
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#endif
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/****************************************************************************
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* Name: lpc17_40_prioritize_syscall
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*
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* Description:
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* Set the priority of an exception. This function may be needed
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* internally even if support for prioritized interrupts is not enabled.
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*
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****************************************************************************/
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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static inline void lpc17_40_prioritize_syscall(int priority)
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{
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uint32_t regval;
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/* SVCALL is system handler 11 */
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regval = getreg32(NVIC_SYSH8_11_PRIORITY);
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regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
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regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
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putreg32(regval, NVIC_SYSH8_11_PRIORITY);
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}
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#endif
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/****************************************************************************
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* Name: lpc17_40_irqinfo
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*
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* Description:
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* Given an IRQ number, provide the register and bit setting to enable or
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* disable the irq.
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*
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****************************************************************************/
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static int lpc17_40_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
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uintptr_t offset)
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{
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DEBUGASSERT(irq >= LPC17_40_IRQ_NMI && irq < NR_IRQS);
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/* Check for external interrupt */
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if (irq >= LPC17_40_IRQ_EXTINT)
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{
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if (irq < (LPC17_40_IRQ_EXTINT+32))
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{
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*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
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*bit = 1 << (irq - LPC17_40_IRQ_EXTINT);
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}
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else if (irq < LPC17_40_IRQ_NIRQS)
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{
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*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
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*bit = 1 << (irq - LPC17_40_IRQ_EXTINT - 32);
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}
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else
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{
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return ERROR; /* Invalid irq */
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}
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}
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/* Handle processor exceptions. Only a few can be disabled */
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else
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{
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*regaddr = NVIC_SYSHCON;
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if (irq == LPC17_40_IRQ_MEMFAULT)
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{
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*bit = NVIC_SYSHCON_MEMFAULTENA;
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}
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else if (irq == LPC17_40_IRQ_BUSFAULT)
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{
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*bit = NVIC_SYSHCON_BUSFAULTENA;
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}
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else if (irq == LPC17_40_IRQ_USAGEFAULT)
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{
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*bit = NVIC_SYSHCON_USGFAULTENA;
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}
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else if (irq == LPC17_40_IRQ_SYSTICK)
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{
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*regaddr = NVIC_SYSTICK_CTRL;
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*bit = NVIC_SYSTICK_CTRL_ENABLE;
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}
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else
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{
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return ERROR; /* Invalid or unsupported exception */
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}
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}
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_irqinitialize
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****************************************************************************/
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void up_irqinitialize(void)
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{
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uintptr_t regaddr;
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int nintlines;
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int i;
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/* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
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* lines that the NVIC supports, defined in groups of 32. That is,
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* the total number of interrupt lines is up to (32*(INTLINESNUM+1)).
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*
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* 0 -> 32 interrupt lines, 1 enable register, 8 priority registers
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* 1 -> 64 " " " ", 2 enable registers, 16 priority registers
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* 2 -> 96 " " " ", 3 enable regsiters, 24 priority registers
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* ...
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*/
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nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1;
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/* Disable all interrupts. There are nintlines interrupt enable
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* registers.
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*/
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for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR;
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i > 0;
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i--, regaddr += 4)
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{
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putreg32(0xffffffff, regaddr);
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}
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/* Make sure that we are using the correct vector table. The default
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* vector address is 0x0000:0000 but if we are executing code that is
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* positioned in SRAM or in external FLASH, then we may need to reset
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* the interrupt vector so that it refers to the table in SRAM or in
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* external FLASH.
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*/
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putreg32((uint32_t)_vectors, NVIC_VECTAB);
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/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
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* vector table that requires special initialization.
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*
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* But even in this case NVIC_VECTAB has to point to the initial table
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* because up_ramvec_initialize() initializes RAM table from table
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* pointed by NVIC_VECTAB register.
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*/
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#ifdef CONFIG_ARCH_RAMVECTORS
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up_ramvec_initialize();
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#endif
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/* Set all interrupts (and exceptions) to the default priority */
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putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
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putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
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/* Now set all of the interrupt lines to the default priority. There are
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* nintlines * 8 priority registers.
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*/
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for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY;
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i > 0;
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i--, regaddr += 4)
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{
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putreg32(DEFPRIORITY32, regaddr);
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}
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/* currents_regs is non-NULL only while processing an interrupt */
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CURRENT_REGS = NULL;
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/* Attach the SVCall and Hard Fault exception handlers. The SVCall
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* exception is used for performing context switches; The Hard Fault
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* must also be caught because a SVCall may show up as a Hard Fault
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* under certain conditions.
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*/
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irq_attach(LPC17_40_IRQ_SVCALL, up_svcall, NULL);
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irq_attach(LPC17_40_IRQ_HARDFAULT, up_hardfault, NULL);
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/* Set the priority of the SVCall interrupt */
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#ifdef CONFIG_ARCH_IRQPRIO
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/* up_prioritize_irq(LPC17_40_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
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#endif
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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lpc17_40_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
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#endif
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/* If the MPU is enabled, then attach and enable the Memory Management
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* Fault handler.
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*/
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#ifdef CONFIG_ARM_MPU
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irq_attach(LPC17_40_IRQ_MEMFAULT, up_memfault, NULL);
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up_enable_irq(LPC17_40_IRQ_MEMFAULT);
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#endif
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/* Attach all other processor exceptions (except reset and sys tick) */
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#ifdef CONFIG_DEBUG_FEATURES
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irq_attach(LPC17_40_IRQ_NMI, lpc17_40_nmi, NULL);
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#ifndef CONFIG_ARM_MPU
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irq_attach(LPC17_40_IRQ_MEMFAULT, up_memfault, NULL);
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#endif
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irq_attach(LPC17_40_IRQ_BUSFAULT, lpc17_40_busfault, NULL);
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irq_attach(LPC17_40_IRQ_USAGEFAULT, lpc17_40_usagefault, NULL);
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irq_attach(LPC17_40_IRQ_PENDSV, lpc17_40_pendsv, NULL);
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irq_attach(LPC17_40_IRQ_DBGMONITOR, lpc17_40_dbgmonitor, NULL);
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irq_attach(LPC17_40_IRQ_RESERVED, lpc17_40_reserved, NULL);
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#endif
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lpc17_40_dumpnvic("initial", LPC17_40_IRQ_NIRQS);
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/* Initialize logic to support a second level of interrupt decoding for
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* GPIO pins.
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*/
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#ifdef CONFIG_LPC17_40_GPIOIRQ
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lpc17_40_gpioirqinitialize();
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#endif
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/* And finally, enable interrupts */
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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up_irq_enable();
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#endif
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}
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/****************************************************************************
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* Name: up_disable_irq
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*
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* Description:
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* Disable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_disable_irq(int irq)
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{
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uintptr_t regaddr;
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uint32_t regval;
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uint32_t bit;
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if (lpc17_40_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0)
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{
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/* Modify the appropriate bit in the register to disable the interrupt.
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* For normal interrupts, we need to set the bit in the associated
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* Interrupt Clear Enable register. For other exceptions, we need to
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* clear the bit in the System Handler Control and State Register.
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*/
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if (irq >= LPC17_40_IRQ_EXTINT)
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{
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putreg32(bit, regaddr);
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}
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else
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{
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regval = getreg32(regaddr);
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regval &= ~bit;
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putreg32(regval, regaddr);
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}
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}
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#ifdef CONFIG_LPC17_40_GPIOIRQ
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else if (irq >= LPC17_40_VALID_FIRST0L)
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{
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/* Maybe it is a (derived) GPIO IRQ */
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lpc17_40_gpioirqdisable(irq);
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}
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#endif
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lpc17_40_dumpnvic("disable", irq);
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}
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/****************************************************************************
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* Name: up_enable_irq
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*
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* Description:
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* Enable the IRQ specified by 'irq'
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*
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****************************************************************************/
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void up_enable_irq(int irq)
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{
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uintptr_t regaddr;
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uint32_t regval;
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uint32_t bit;
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if (lpc17_40_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0)
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{
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/* Modify the appropriate bit in the register to enable the interrupt.
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* For normal interrupts, we need to set the bit in the associated
|
|
* Interrupt Set Enable register. For other exceptions, we need to
|
|
* set the bit in the System Handler Control and State Register.
|
|
*/
|
|
|
|
if (irq >= LPC17_40_IRQ_EXTINT)
|
|
{
|
|
putreg32(bit, regaddr);
|
|
}
|
|
else
|
|
{
|
|
regval = getreg32(regaddr);
|
|
regval |= bit;
|
|
putreg32(regval, regaddr);
|
|
}
|
|
}
|
|
#ifdef CONFIG_LPC17_40_GPIOIRQ
|
|
else if (irq >= LPC17_40_VALID_FIRST0L)
|
|
{
|
|
/* Maybe it is a (derived) GPIO IRQ */
|
|
|
|
lpc17_40_gpioirqenable(irq);
|
|
}
|
|
#endif
|
|
|
|
lpc17_40_dumpnvic("enable", irq);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: up_ack_irq
|
|
*
|
|
* Description:
|
|
* Acknowledge the IRQ
|
|
*
|
|
****************************************************************************/
|
|
|
|
void up_ack_irq(int irq)
|
|
{
|
|
#if 0 /* Does not appear to be necessary in most cases */
|
|
lpc17_40_clrpend(irq);
|
|
#endif
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: up_prioritize_irq
|
|
*
|
|
* Description:
|
|
* Set the priority of an IRQ.
|
|
*
|
|
* Since this API is not supported on all architectures, it should be
|
|
* avoided in common implementations where possible.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_ARCH_IRQPRIO
|
|
int up_prioritize_irq(int irq, int priority)
|
|
{
|
|
uint32_t regaddr;
|
|
uint32_t regval;
|
|
int shift;
|
|
|
|
DEBUGASSERT(irq >= LPC17_40_IRQ_MEMFAULT && irq < LPC17_40_IRQ_NIRQS &&
|
|
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
|
|
|
if (irq < LPC17_40_IRQ_EXTINT)
|
|
{
|
|
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
|
|
* registers (0-3 are invalid)
|
|
*/
|
|
|
|
regaddr = NVIC_SYSH_PRIORITY(irq);
|
|
irq -= 4;
|
|
}
|
|
else
|
|
{
|
|
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
|
|
|
|
irq -= LPC17_40_IRQ_EXTINT;
|
|
regaddr = NVIC_IRQ_PRIORITY(irq);
|
|
}
|
|
|
|
regval = getreg32(regaddr);
|
|
shift = ((irq & 3) << 3);
|
|
regval &= ~(0xff << shift);
|
|
regval |= (priority << shift);
|
|
putreg32(regval, regaddr);
|
|
|
|
lpc17_40_dumpnvic("prioritize", irq);
|
|
return OK;
|
|
}
|
|
#endif
|