4c601faf6f
Squashed commit of the following:
arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions.
arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0.
arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0.
arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts.
arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls.
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file.
arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file.
arch/arm/include/stm32f0l0/chip.h: WIP.
arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options.
arch/arm/src/stm32f0l0: Better integrate STM32L0 header files.
nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file.
arch/arm/src/stm32f0l0: Add STM32L0 RCC driver.
arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files.
arch/arm/src/stm32f0l0: Add STM32L0 chip selections.
configs/: Hook new STM32L0 boards into the configuration system.
configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled
configs: add basic support for nucleo-l073rz
configs: add basic support for b-l072z-lrwan1
125 lines
3.6 KiB
Plaintext
125 lines
3.6 KiB
Plaintext
/****************************************************************************
|
|
* configs/b-l072z-lrwan1/scripts/ld.script
|
|
*
|
|
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
|
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
*
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in
|
|
* the documentation and/or other materials provided with the
|
|
* distribution.
|
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
|
* used to endorse or promote products derived from this software
|
|
* without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
* POSSIBILITY OF SUCH DAMAGE.
|
|
*
|
|
****************************************************************************/
|
|
|
|
/* The STM32LO72CZ has 192Kb of FLASH beginning at address 0x0800:0000.
|
|
* 20Kb of SRAM and 6Kb of EEPROM
|
|
*
|
|
* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
|
|
* where the code expects to begin execution by jumping to the entry point in
|
|
* the 0x0800:0000 address range.
|
|
*/
|
|
|
|
MEMORY
|
|
{
|
|
flash (rx) : ORIGIN = 0x08000000, LENGTH = 192K
|
|
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
|
|
}
|
|
|
|
OUTPUT_ARCH(arm)
|
|
EXTERN(_vectors)
|
|
ENTRY(_stext)
|
|
SECTIONS
|
|
{
|
|
.text : {
|
|
_stext = ABSOLUTE(.);
|
|
*(.vectors)
|
|
*(.text .text.*)
|
|
*(.fixup)
|
|
*(.gnu.warning)
|
|
*(.rodata .rodata.*)
|
|
*(.gnu.linkonce.t.*)
|
|
*(.glue_7)
|
|
*(.glue_7t)
|
|
*(.got)
|
|
*(.gcc_except_table)
|
|
*(.gnu.linkonce.r.*)
|
|
_etext = ABSOLUTE(.);
|
|
} > flash
|
|
|
|
.init_section : {
|
|
_sinit = ABSOLUTE(.);
|
|
*(.init_array .init_array.*)
|
|
_einit = ABSOLUTE(.);
|
|
} > flash
|
|
|
|
.ARM.extab : {
|
|
*(.ARM.extab*)
|
|
} > flash
|
|
|
|
__exidx_start = ABSOLUTE(.);
|
|
.ARM.exidx : {
|
|
*(.ARM.exidx*)
|
|
} > flash
|
|
__exidx_end = ABSOLUTE(.);
|
|
|
|
_eronly = ABSOLUTE(.);
|
|
|
|
/* The RAM vector table (if present) should lie at the beginning of SRAM */
|
|
|
|
.ram_vectors : {
|
|
*(.ram_vectors)
|
|
} > sram
|
|
|
|
.data : {
|
|
_sdata = ABSOLUTE(.);
|
|
*(.data .data.*)
|
|
*(.gnu.linkonce.d.*)
|
|
CONSTRUCTORS
|
|
_edata = ABSOLUTE(.);
|
|
} > sram AT > flash
|
|
|
|
.bss : {
|
|
_sbss = ABSOLUTE(.);
|
|
*(.bss .bss.*)
|
|
*(.gnu.linkonce.b.*)
|
|
*(COMMON)
|
|
_ebss = ABSOLUTE(.);
|
|
} > sram
|
|
|
|
/* Stabs debugging sections. */
|
|
.stab 0 : { *(.stab) }
|
|
.stabstr 0 : { *(.stabstr) }
|
|
.stab.excl 0 : { *(.stab.excl) }
|
|
.stab.exclstr 0 : { *(.stab.exclstr) }
|
|
.stab.index 0 : { *(.stab.index) }
|
|
.stab.indexstr 0 : { *(.stab.indexstr) }
|
|
.comment 0 : { *(.comment) }
|
|
.debug_abbrev 0 : { *(.debug_abbrev) }
|
|
.debug_info 0 : { *(.debug_info) }
|
|
.debug_line 0 : { *(.debug_line) }
|
|
.debug_pubnames 0 : { *(.debug_pubnames) }
|
|
.debug_aranges 0 : { *(.debug_aranges) }
|
|
}
|