Huang Qi 040e1379cd riscv_vector.S: Align trap vector to 64 byte ...

Bump align to 64 byte to support all interrupt mode, it is essential for CLIC.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>

2024-06-21 03:02:59 +08:00

..

include

riscv: Add indirect CSRs for CLIC

2024-06-21 03:02:59 +08:00

src

riscv_vector.S: Align trap vector to 64 byte

2024-06-21 03:02:59 +08:00

CMakeLists.txt

cmake:init RISC-V cmake qemu-rv build

2023-10-26 21:01:46 +08:00

Kconfig

arch/risc-v: Add support for SOPHGO SG2000 SoC (T-Head C906)

2024-06-17 09:41:29 +08:00