375 lines
12 KiB
C
375 lines
12 KiB
C
/****************************************************************************
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* arch/arm/src/chip/sam_clockconfig.c
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*
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* Copyright (C) 2010, 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "sam_clockconfig.h"
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#include "chip/sam_pmc.h"
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#include "chip/sam_eefc.h"
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#include "chip/sam_wdt.h"
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#include "chip/sam_supc.h"
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#include "chip/sam_matrix.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* PMC register settings based on the board configuration values defined
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* in board.h
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*/
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#define BOARD_CKGR_MOR (PMC_CKGR_MOR_KEY | BOARD_CKGR_MOR_MOSCXTST | \
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PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN)
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#if defined(CONFIG_ARCH_CHIP_SAM3U)
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# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \
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BOARD_CKGR_PLLAR_STMODE | BOARD_CKGR_PLLAR_COUNT | \
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BOARD_CKGR_PLLAR_DIV)
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#elif defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM3X)
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# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \
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BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV)
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#elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
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# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \
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BOARD_CKGR_PLLAR_COUNT | BOARD_CKGR_PLLAR_DIV)
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#endif
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#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES | PMC_MCKR_CSS_MAIN)
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#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES | BOARD_PMC_MCKR_CSS)
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#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT | PMC_CKGR_UCKR_UPLLEN)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: sam_efcsetup
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*
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* Description:
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* Configure 2 waitstates for embedded flash access
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*
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****************************************************************************/
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static inline void sam_efcsetup(void)
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{
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putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC0_FMR);
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#if !defined(CONFIG_ARCH_CHIP_SAM4E)
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putreg32((BOARD_FWS << EEFC_FMR_FWS_SHIFT), SAM_EEFC1_FMR);
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#endif
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}
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/****************************************************************************
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* Name: sam_wdtsetup
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*
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* Description:
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* Disable the watchdog timer
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*
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****************************************************************************/
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static inline void sam_wdtsetup(void)
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{
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putreg32(WDT_MR_WDDIS, SAM_WDT_MR);
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}
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/****************************************************************************
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* Name: sam_supcsetup
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*
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* Description:
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* Select the external slow clock
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*
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****************************************************************************/
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static inline void sam_supcsetup(void)
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{
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/* Check if the 32-kHz is already selected */
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if ((getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0)
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{
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uint32_t delay;
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putreg32((SUPC_CR_XTALSEL|SUPR_CR_KEY), SAM_SUPC_CR);
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for (delay = 0;
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(getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX;
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delay++);
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}
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}
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/****************************************************************************
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* Name: sam_pmcwait
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*
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* Description:
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* Wait for the specified PMC status bit to become "1"
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*
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****************************************************************************/
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static void sam_pmcwait(uint32_t bit)
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{
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volatile uint32_t delay;
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for (delay = 0;
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(getreg32(SAM_PMC_SR) & bit) == 0 && delay < UINT32_MAX;
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delay++);
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}
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/****************************************************************************
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* Name: sam_pmcsetup
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*
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* Description:
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* Initialize clocking
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*
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****************************************************************************/
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static inline void sam_pmcsetup(void)
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{
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uint32_t regval;
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/* Enable main oscillator (if it has not already been selected) */
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if ((getreg32(SAM_PMC_CKGR_MOR) & PMC_CKGR_MOR_MOSCSEL) == 0)
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{
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/* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to
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* enable the main oscillator, the MOSCXTS bit in the Power Management
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* Controller Status Register (PMC_SR) is cleared and the counter starts
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* counting down on the slow clock divided by 8 from the MOSCXTCNT
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* value. ... When the counter reaches 0, the MOSCXTS bit is set,
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* indicating that the main clock is valid."
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*/
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putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR);
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sam_pmcwait(PMC_INT_MOSCXTS);
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}
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/* "Switch to the main oscillator. The selection is made by writing the
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* MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of
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* the Main Clock source is glitch free, so there is no need to run out
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* of SLCK, PLLACK or UPLLCK in order to change the selection. The MOSCSELS
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* bit of the power Management Controller Status Register (PMC_SR) allows
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* knowing when the switch sequence is done."
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*
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* MOSCSELS: Main Oscillator Selection Status
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* 0 = Selection is done
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* 1 = Selection is in progress
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*/
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putreg32((BOARD_CKGR_MOR | PMC_CKGR_MOR_MOSCSEL), SAM_PMC_CKGR_MOR);
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sam_pmcwait(PMC_INT_MOSCSELS);
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/* "Select the master clock. "The Master Clock selection is made by writing
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* the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register).
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* The prescaler supports the division by a power of 2 of the selected clock
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* between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs
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* the prescaler. Each time PMC_MCKR is written to define a new Master Clock,
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* the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is
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* established.
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*/
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regval = getreg32(SAM_PMC_MCKR);
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regval &= ~PMC_MCKR_CSS_MASK;
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regval |= PMC_MCKR_CSS_MAIN;
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putreg32(regval, SAM_PMC_MCKR);
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sam_pmcwait(PMC_INT_MCKRDY);
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#if defined(CONFIG_ARCH_CHIP_SAM4E)
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/* Setup the maximum value for the PLLAR multiplier. The PMMR register
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* "defines the maximum value of multiplication factor that can be sent to
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* PLLA. Any value of the MULA bitfield ... above PLLA_MMAX is saturated
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* to PLLA_MMAX.
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*/
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//putreg32(PMC_PMMR_MASK, SAM_PMC_PMMR);
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#endif
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/* Setup PLLA and wait for LOCKA */
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putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
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sam_pmcwait(PMC_INT_LOCKA);
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#ifdef CONFIG_USBDEV
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/* Setup UTMI for USB and wait for LOCKU */
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#ifdef SAM_PMC_CKGR_UCKR
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/* This MCU has a USB PLL. Configure the UPLL and wait for it to lock. */
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regval = getreg32(SAM_PMC_CKGR_UCKR);
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regval |= BOARD_CKGR_UCKR;
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putreg32(regval, SAM_PMC_CKGR_UCKR);
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sam_pmcwait(PMC_INT_LOCKU);
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#else
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/* This board does not have a UPLL. Use the output of PLLA or PLLA
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* (depending on USBS) and setup the PLL divisor to generate the 48MHz
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* USB clock.
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*/
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regval = (BOARD_PMC_USBS | BOARD_PMC_USBDIV);
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putreg32(regval, SAM_PMC_USB);
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#if 0 /* Done in the UDP driver */
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/* Set the UDP bit in the SCER register to enable the USB clock output */
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regval = getreg32(SAM_PMC_SCER);
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regval |= PMC_UDP;
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putreg32(regval, SAM_PMC_SCER);
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#endif /* 0 */
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#endif /* SAM_PMC_CKGR_UCKR */
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#endif /* CONFIG_USBDEV */
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/* Switch to the fast clock and wait for MCKRDY */
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putreg32(BOARD_PMC_MCKR_FAST, SAM_PMC_MCKR);
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sam_pmcwait(PMC_INT_MCKRDY);
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putreg32(BOARD_PMC_MCKR, SAM_PMC_MCKR);
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sam_pmcwait(PMC_INT_MCKRDY);
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}
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/****************************************************************************
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* Name: sam_enabledefaultmaster and sam_disabledefaultmaster
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*
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* Description:
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* Enable/disable default master access
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*
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****************************************************************************/
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static inline void sam_enabledefaultmaster(void)
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{
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uint32_t regval;
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/* Set default master: SRAM0 -> Cortex-M3 System */
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regval = getreg32(SAM_MATRIX_SCFG0);
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regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
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putreg32(regval, SAM_MATRIX_SCFG0);
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/* Set default master: SRAM1 -> Cortex-M3 System */
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regval = getreg32(SAM_MATRIX_SCFG1);
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regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
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putreg32(regval, SAM_MATRIX_SCFG1);
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/* Set default master: Internal flash0 -> Cortex-M3 Instruction/Data */
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regval = getreg32(SAM_MATRIX_SCFG3);
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regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
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putreg32(regval, SAM_MATRIX_SCFG3);
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}
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#if 0 /* Not used */
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static inline void sam_disabledefaultmaster(void)
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{
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uint32_t regval;
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/* Clear default master: SRAM0 -> Cortex-M3 System */
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regval = getreg32(SAM_MATRIX_SCFG0);
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regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
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putreg32(regval, SAM_MATRIX_SCFG0);
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/* Clear default master: SRAM1 -> Cortex-M3 System */
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regval = getreg32(SAM_MATRIX_SCFG1);
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regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
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putreg32(regval, SAM_MATRIX_SCFG1);
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/* Clear default master: Internal flash0 -> Cortex-M3 Instruction/Data */
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regval = getreg32(SAM_MATRIX_SCFG3);
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regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
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putreg32(regval, SAM_MATRIX_SCFG3);
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/************************************************************************************
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* Name: sam_clockconfig
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*
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* Description:
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* Called to initialize the SAM3/4. This does whatever setup is needed to put the
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* SoC in a usable state. This includes the initialization of clocking using the
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* settings in board.h. (After power-on reset, the SAM3/4 is initially running on
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* a 4MHz internal RC clock). This function also performs other low-level chip
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* initialization of the chip including EFC, master clock, IRQ & watchdog
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* configuration.
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*
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************************************************************************************/
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void sam_clockconfig(void)
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{
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/* Configure embedded flash access */
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sam_efcsetup();
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/* Configure the watchdog timer */
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sam_wdtsetup();
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/* Setup the supply controller to use the external slow clock */
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sam_supcsetup();
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/* Initialize clocking */
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sam_pmcsetup();
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/* Optimize CPU setting for speed */
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sam_enabledefaultmaster();
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}
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