ligd 059497d1d1 armv7-a/r: NON-primary core should invalidate dacache level1 ... NON-primary cpu will invalidate cpu0's cache L2, that will caused cpu0's data mismatch, and then system crash Signed-off-by: ligd <liguiding1@xiaomi.com>		2022-09-27 14:41:39 +08:00
..
include	libc: Move queue.h from include to include/nuttx	2022-09-26 08:04:58 +02:00
src	armv7-a/r: NON-primary core should invalidate dacache level1	2022-09-27 14:41:39 +08:00
Kconfig	arch/arm: initial support for NRF5340	2022-09-18 21:49:32 +08:00